Vertical field effect transistor device and method of fabrication
A method and vertical FET device fabricated in GaN or other suitable material. The device has a selective area implant region comprising an activated impurity configured from a bottom portion of a recessed regions, and substantially free from ion implant damage by using an annealing process. A p-type gate region is configured from the selective area implant region, and each of the recessed regions is characterized by a depth configured to physically separate an n+ type source region and the p-type gate region such that a low reverse leakage gate-source p-n junction is achieved. An extended drain region is configured from a portion of an n-type GaN region underlying the recessed regions. An n+ GaN region is formed by epitaxial growth directly overlying the backside region of the GaN substrate and a backside drain contact region configured from the n+ type GaN region overlying the backside region.
1 . A method of fabricating a vertical FET device fabricated in GaN, the method comprising:
providing a GaN substrate comprising a surface region and a backside region;
forming an n-type GaN epitaxial layer overlying the surface region;
forming a plurality of finger regions, each of the finger regions having a portion of the n− type GaN epitaxial layer, an n+ type portion; and a capping layer; and configured with a plurality of recessed regions, each of the recessed regions between each pair of finger regions;
forming an n-type GaN channel comprising a doping level and a thickness selected to provide a large gate-drain breakdown voltage in a range from 100 volts to 20 kilo-volts;
forming an n+ type source configured from the n+ type portion of the finger region;
performing a selective area implant region comprising an activated impurity, the activated impurity being selected from at least one of Be, Mg, Zn, Ca, or Cd, configured from a bottom portion of the recessed regions;
forming a p-type gate region configured from the selective area implant region;
forming a depth characterizing each of the recessed regions configured to provide physical separation between the n+ type source region and the p-type gate region;
forming an extended drain region configured from a portion of n-type GaN region underlying the recessed regions;
forming an n+ GaN region formed by epitaxial growth directly overlying the backside region of the GaN substrate; and
forming a backside drain contact region configured from the n+ type GaN region overlying the backside region.
2 . The method of claim 1 wherein the n+ source region or regions are provided by a donor impurity ion implantation and a subsequent annealing process.
3 . The method of claim 1 wherein the n+ source region or regions are provided with silicon as a donor impurity.
4 . The method of claim 1 wherein a channel region or regions are provided with silicon as a donor impurity.
5 . The method of claim 1 further comprising a built-in voltage of a gate-source diode is approximately 3 volts to achieve a wider channel width as compared to a metal-insulator-semiconductor gate structure for a normally-off enhancement mode device.
6 . The method of claim 1 further comprising a dielectric spacer layer deposited conformally overlying the recessed regions to limit a lateral penetration of a subsequent ion implant of acceptors into the n-type GaN channel.
7 . The method of claim 1 further comprising a dielectric spacer layer deposited conformally overlying the recessed regions to encapsulate and passivate a plurality of GaN exposed surfaces between the n+ type source and the p-type gate region.
8 . The method of claim 1 further comprising a trench region configured around a periphery of a device region, the trench region comprising a dielectric fill material and configured to form an isolation region.
9 . The method of claim 8 wherein the dielectric fill material is at least one of SiN, a mixed dielectric AlSiN, or AlN.
10 . The method of claim 1 wherein the GaN substrate is n+ type.
11 . A method of fabricating a vertical FET device fabricated in GaN, the method comprising:
providing a GaN substrate comprising a surface region and a backside region;
forming an n− type GaN epitaxial layer overlying the surface region;
forming a plurality of finger regions, each of the finger regions having a portion of the n− type GaN epitaxial layer, an n+ type portion and a capping layer, and configured with a plurality of recessed regions, each of the recessed regions between each pair of finger regions;
forming an n− type GaN channel comprising a doping level and a thickness selected to provide a large gate-drain breakdown voltage in a range from 100 volts to 20 kilo-volts;
forming an n+ type source configured from the n+ type portion of the finger region;
performing a selective area implant region comprising an activated impurity, the activated impurity being selected from at least one of Be, Mg, Zn, Ca, or Cd, configured from a bottom portion of the recessed regions;
forming a p-type gate region configured from the selective area implant region;
forming a depth characterizing each of the recessed regions configured to provide physical separation between the n+ type source region and the p-type gate region such that a low reverse leakage gate-source p-n junction is achieved, and an extended drain region configured from a portion of n− type GaN region underlying the recessed regions;
forming an n+ GaN region formed by epitaxial growth directly overlying the backside region of the GaN substrate; and
forming a backside drain contact region configured from the n+ type GaN region overlying the backside region.
12 . The method of claim 11 wherein the n+ source region or regions are provided by a donor impurity ion implantation and a subsequent annealing process.
13 . The method of claim 11 wherein the n+ source region or regions are provided with silicon as a donor impurity.
14 . The method of claim 11 wherein a channel region or regions are provided with silicon as a donor impurity.
15 . The method of claim 11 further comprising a built-in voltage of a gate-source diode is approximately 3 volts to achieve a wider channel width as compared to a metal-insulator-semiconductor gate structure for a normally-off enhancement mode device.
16 . The method of claim 11 further comprising a dielectric spacer layer deposited conformally overlying the recessed regions to limit a lateral penetration of a subsequent ion implant of acceptors into the n− type GaN channel.
17 . The method of claim 11 further comprising a dielectric spacer layer deposited conformally overlying the recessed regions to encapsulate and passivate a plurality of GaN exposed surfaces between the n+ type source and the p-type gate region.
18 . The method of claim 11 further comprising a trench region configured around a periphery of a device region, the trench region comprising a dielectric fill material and configured to form an isolation region.
19 . The method of claim 18 wherein the dielectric fill material is at least one of SiN, a mixed dielectric AlSiN, or AlN.
20 . The method of claim 11 wherein the GaN substrate is n+ type.