Magnetic memory device
A magnetic memory device according to an embodiment includes a magnetic memory device includes first and second interconnect, a memory cell, a transistor, first and second sense amplifiers, and a control circuit. The memory cell includes a magnetoresistive effect element and a selector element. The magnetoresistive effect element and the selector element are coupled in series between the first and second interconnect. In a read operation, the control circuit is further configured to: charge the first interconnect to a first voltage; and discharge the first interconnect via the transistor by applying a second voltage to a gate end of the transistor.
1 . A magnetic memory device comprising:
a first interconnect;
a second interconnect;
a memory cell that includes a magnetoresistive effect element and a selector element, the magnetoresistive effect element and the selector element being coupled in series between the first interconnect and the second interconnect;
a transistor coupled between the second interconnect and a ground node;
a first sense amplifier configured to amplify a voltage difference between the first interconnect and the second interconnect;
a second sense amplifier configured to determine data stored in the memory cell based on a result of comparing an output voltage of the first sense amplifier with a reference voltage; and
a control circuit configured to perform a read operation, wherein
in the read operation, the control circuit is further configured to:
charge the first interconnect to a first voltage; and
discharge, after charging the first interconnect, the first interconnect via the transistor by applying a second voltage to a gate end of the transistor, wherein the transistor to which the second voltage is applied limits a current flowing between one end and the other end of the transistor to a first current; and
causes the first sense amplifier to amplify a voltage difference between the first interconnect that has been discharged via the transistor and the second interconnect and causes the second sense amplifier to determine data stored in the memory cell.
2 . The magnetic memory device of claim 1 , wherein
the second voltage is a voltage between a first logic level voltage and a second logic level, the second logic level being a reverse logic level of the first logic level.
3 . The magnetic memory device of claim 1 , wherein
at a first time after discharging of the first interconnect is started in the read operation, a voltage difference between the first interconnect and the second interconnect is, if the magnetoresistive effect element included in the memory cell is in a parallel state, a first determination voltage, and if the magnetoresistive effect element included in the memory cell is in an anti-parallel state, a second determination voltage higher than the first determination voltage, and
a voltage between the first determination voltage and the second determination voltage is greater in a case where the first current flows in the memory cell than in a case where a second current smaller than the first current flows in the memory cell and a case where a third current larger than the first current flows in the memory cell.
4 . The magnetic memory device of claim 3 , wherein
the difference is greatest if the first current flows in the memory cell.
5 . The magnetic memory device of claim 1 , wherein
the magnetoresistive effect element is further configured to change between a parallel state and an anti-parallel state if a current equal to or greater than a fourth current flows, and
the first current is smaller than the fourth current.
6 . The magnetic memory device of claim 1 , wherein
the fourth current is 40 to 80 μA.
7 . The magnetic memory device of claim 1 , wherein
the magnetoresistive effect element is configured to allow a tunnel barrier destruction to occur when a current equal to or greater than a fifth current flows,
the first current is smaller than the fifth current.
8 . The magnetic memory device of claim 7 , wherein
the fifth current is 250 to 80 μA.
9 . The magnetic memory device of claim 1 , wherein
in the read operation, the control circuit is further configured to:
apply the second voltage to a gate end of the transistor in a first period during which the second sense amplifier determines, after the first interconnect is charged, data stored in the memory cell; and
apply a third voltage higher than the second voltage to a gate end of the transistor in a period after the first interconnect is charged except for the first period.
10 . The magnetic memory device of claim 1 , further comprising:
a switch circuit coupled to the transistor in parallel, wherein
in the read operation, the control circuit is further configured to:
control the switch circuit to be in an off state in a period during which the second sense amplifier determines data; and
control the switch circuit to be in an on state in a period other than a period during which the second sense amplifier determines data.