Fabrication method for JFET with implant isolation
Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.
1. A method of manufacturing a vertical junction field effect transistor (JFET), the method comprising:
providing a semiconductor substrate of a first conductivity type and having a first surface and a second surface;
forming a plurality of fins of the first conductivity type coupled to the semiconductor substrate;
forming a gate layer of a second conductivity type opposite the first conductivity type surrounding the plurality of fins;
forming an isolation region surrounding the plurality of fins; and
forming a diode region surrounding the isolation region.
2. The method of claim 1 , wherein forming the isolation region comprises forming a trench within the gate layer.
3. The method of claim 2 , wherein:
forming the trench comprises forming the trench comprising a first width;
forming the plurality of fins comprises providing each of the plurality of fins with a second width; and
the first width is less than the second width.
4. The method of claim 2 , further comprising:
providing a dielectric within the trench.
5. The method of claim 1 , wherein forming the isolation region comprises forming floating fin electrically decoupled from the plurality of fins.
6. The method of claim 1 , wherein forming the isolation region comprises forming a doped region of the first conductivity type within the gate layer.
7. The method of claim 1 , further comprising:
electrically coupling the diode region to the plurality of fins.
8. The method of claim 1 , wherein forming the isolation region and forming the diode region comprises concurrently forming the isolation region and forming the diode region in a portion of the gate layer.
9. The method of claim 1 , wherein:
forming the diode region comprises providing an MPS diode;
the gate layer provides an anode of the MPS diode; and
the semiconductor substrate provides a cathode of the MPS diode.
10. The method of claim 1 , wherein:
forming the diode region comprises providing the diode region in a portion of the gate layer;
the method further comprises providing a region of semiconductor material of the first conductivity type in the portion of the gate layer; and
forming the diode region comprises providing a Schottky diode using the region of semiconductor material.
11. The method of claim 1 , wherein:
forming the gate layer comprises depositing the gate layer using one or more of metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).
12. The method of claim 1 , wherein forming the plurality of fins comprise:
providing a first semiconductor region of the first conductivity type over the semiconductor substrate; and
selectively removing portions of the first semiconductor region to form the plurality of fins.
13. A method of forming a vertical junction field effect transistor (JFET), comprising:
providing a substrate of a first conductivity type;
providing an active region comprising semiconductor fins;
providing a gate region of a second conductivity type opposite to the first conductivity type adjacent to the semiconductor fins;
providing a first conductor electrically coupled to a surface of each of the semiconductor fins;
providing an isolation region surrounding the active region;
providing a diode region surrounding the isolation region;
providing a first conductive pad electrically coupled to the first conductor and the diode region; and
providing a second conductive pad electrically coupled to the gate region.
14. The method of claim 13 , wherein:
providing the substrate comprises:
providing a semiconductor substrate comprising a first surface, a second surface opposite to the first surface, and a semiconductor region of the first conductivity type over the first surface of the semiconductor substrate;
providing the active region comprises;
selectively removing portions of the semiconductor region to form the semiconductor fins surrounded by a recessed region; and
providing the gate region comprises providing the gate region within the recessed region using one more of metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).
15. The method of claim 14 , wherein;
providing the semiconductor region comprises:
providing a first III-nitride portion adjacent to the first surface of the semiconductor substrate comprising a first dopant concentration; and
providing a second III-nitride portion over the first III-nitride portion comprising a second dopant concentration greater than the first dopant concentration.
16. The method of claim 13 , wherein:
providing the diode region comprises providing the diode region within a portion of the gate region isolated from the active region by the isolation region;
the portion of the gate region forms a cathode of an MPS diode in the diode region; and
providing the first conductive pad comprises electrically coupling the first conductive pad to the cathode.
17. The method of claim 13 , wherein:
providing the isolation region comprising forming a trench within a portion of the gate region.