METHOD FOR DICING A SEMICONDUCTOR WAFER
A wafer includes a semiconductor substrate, an interconnection network provided with metal layers and at least one ultra-low dielectric constant dielectric layer, at least one contact region and at least one dicing region. A hard mask is formed having a pattern that defines a dicing line. The formation of the hard mask includes a first etching of an opening in the dicing region to expose the semiconductor substrate in the dicing region, a second etching of an opening in the contact region to expose a surface of a metal contact in the contact region, and a chemical treatment for cleaning the uncovered surface of the metal contact. A vertical dielectric layer is deposited to cover edges of the opening defining the dicing line. This layer is deposited before the chemical treatment is performed.
1 . A method for dicing a semiconductor wafer which includes a semiconductor substrate, an interconnection network provided with metal layers and at least one ultra-low dielectric constant dielectric layer, at least one contact region and at least one dicing region, the method comprising forming a hard mask, wherein forming the hard mask comprises:
forming dielectric layers on the semiconductor wafer in the at least one contact region and in the at least one dicing region;
a first etching of an opening in the at least one dicing region extending through said metal layers of the interconnection network;
a second etching of an opening in the at least one contact region uncovering a surface of a metal contact of the interconnection network;
depositing a vertical dielectric layer covering edges of the opening formed by the first etching to defining a dicing line; and
then cleaning the uncovered surface of the metal contact using a chemical treatment.
2 . The method according to claim 1 , wherein said first etching is performed after forming the dielectric layers, with the opening formed by the first etching extending through said dielectric layers and said layers of the interconnection network until the semiconductor substrate is uncovered so as to shape a pattern of the hard mask defining the dicing line.
3 . The method according to claim 2 , wherein the first etching comprises:
forming a specific first temporary mask which covers the dielectric layers in the at least one contact region and uncovers the dielectric layers in the at least one dicing region; and
removing the dielectric layers and said metal layers of the interconnection network in the at least one dicing region until the semiconductor substrate is uncovered in the pattern of the hard mask.
4 . The method according to claim 2 , wherein depositing the vertical dielectric layer comprises depositing a conforming layer of a material selected from the group consisting of silicon nitride and silicon oxide on the entire semiconductor wafer.
5 . The method according to claim 2 , wherein the second etching comprises:
forming a specific temporary mask covering the at least one dicing region and uncovering the dielectric layers in the at least one contact region; and
removing the dielectric layers in the at least one contact region until the surface of the metal contact is uncovered.
6 . The method according to claim 1 , wherein the first etching is performed before forming the dielectric layers.
7 . The method according to claim 6 , wherein the first etching comprises:
forming a specific third temporary mask covering the interconnection network in the at least one contact region and uncovering the interconnection network in the at least one dicing region; and
removing said metal layers of the interconnection network in the at least one dicing region until the semiconductor substrate is uncovered in the at least one dicing region.
8 . The method according to claim 6 , wherein depositing the vertical dielectric layer is performed during said forming the dielectric layers.
9 . The method according to claim 8 , wherein the second etching simultaneously comprises:
removing the dielectric layers in the contact region until the surface of said metal contact is uncovered; and
removing the dielectric layers in the at least one dicing region until the semiconductor substrate is uncovered, so as to shape said pattern of the hard mask defining the dicing line.
10 . The method according to claim 9 , wherein the second etching comprises forming a fourth temporary mask having an opening in the at least one contact region defining the uncovered surface of the metal contact, and an opening in the at least one dicing region defining the pattern of the hard mask such that a vertical portion of the dielectric layers covers the interconnection network laterally on an edge of the at least one dicing region, in the pattern of the hard mask.
11 . The method according to claim 1 , wherein the first etching is carried out by a reactive ion type plasma.
12 . The method according to claim 1 , further comprising plasma dicing of the semiconductor wafer into semiconductor chip devices singulated from one another, said plasma dicing being performed in the dicing line defined by the pattern of the hard mask.
13 . The method according to claim 1 , wherein said at least one dicing region has a width less than 100 μm.
14 . A method, comprising:
performing a first etching to produce a first opening in at least one dicing region that extends through metal layers of an interconnection network;
forming dielectric layers which cover at least one contact region and which are present in the first opening at said at least one dicing region;
performing a second etching, wherein performing the second etching simultaneously comprises:
producing a second opening in the at least one contact region through the dielectric layers to uncover a surface of a metal contact of the interconnection network; and
producing a third opening, aligned with the first opening, at said at least one dicing region through the dielectric layers to uncover a surface of a semiconductor substrate; and
dicing the semiconductor substrate at the location of the third opening using the dielectric layers at sidewalls of the third opening to delimit a dicing line.
15 . The method of claim 14 , further comprising cleaning the uncovered surface of the metal contact using a chemical treatment.
16 . The method of claim 14 , wherein the first etching is carried out by a reactive ion type plasma.
17 . The method of claim 14 , wherein dicing comprise performing a plasma dicing in the dicing line.
18 . A method, comprising:
forming dielectric layers which cover at least one contact region and at least one dicing region;
performing a first etching to produce a first opening in the at least one dicing region that extends through metal layers of an interconnection network;
depositing a buffer layer on sidewalls and a bottom of the first opening;
forming a mask covering the buffer layer at the at least one dicing region, said mask including a mask opening at the at least one contact region;
performing a second etching to produce a second opening in the at least one contact region through the dielectric layers to uncover a surface of a metal contact of the interconnection network;
removing the mask; and
dicing the semiconductor substrate at the location of the first opening using the buffer layer on the sidewalls to delimit a dicing line.
19 . The method of claim 18 , further comprising cleaning the uncovered surface of the metal contact using a chemical treatment.
20 . The method of claim 18 , wherein the first etching is carried out by a reactive ion type plasma.
21 . The method of claim 18 , wherein dicing comprise performing a plasma dicing in the dicing line.