Memory, memory system, program method of memory, and electronic apparatus
The present disclosure discloses a memory, a memory system, a program method of a memory, and an electronic apparatus, relating to the technical field of memories. The memory includes a memory array and a peripheral circuit, wherein the memory array includes memory cells; the peripheral circuit is configured to perform a first program operation on the memory cells, perform a read operation on a memory page through a preset read voltage, and perform a second program operation on the memory cells in a case where a fail bit count read based on the read voltage meets a preset requirement.
1 . A memory, comprising:
a memory array comprising memory cells; and
a peripheral circuit configured to:
perform a first program operation on the memory cells;
perform a read operation on the memory cells;
determine a program result of the first program operation, corresponding to a fail bit count (FBC) read, by one of:
determining the program result based on a first comparison of a first preset number with a difference in a first number of memory cells between two adjacent preset read voltages of a plurality of preset read voltages, wherein the first comparison, between the first preset number and the difference, determines whether error correction of the program result is performed and error-corrected data is received; or
determining the program result based on a second comparison of a second preset number with a second number of memory cells within a preset offset range of a default read level, the plurality of preset read voltages being configured as the default read level, wherein the second comparison, between the second preset number and the second number, determines whether the error correction of the program result is performed and the error-corrected data is received; and
when the fail bit count (FBC) read corresponding to the program result meets a preset requirement, perform a second program operation on the memory cells.
2 . The memory of claim 1 , wherein the peripheral circuit is further configured to:
perform the read operation on the memory cells through the plurality of preset read voltages; and
read the fail bit count based on the plurality of preset read voltages.
3 . The memory of claim 2 , wherein the peripheral circuit is further configured to:
read the first number of memory cells between the two adjacent preset read voltages of the plurality of preset read voltages; and
determine the fail bit count based on the first number of memory cells between the two adjacent preset read voltages.
4 . The memory of claim 3 , wherein the peripheral circuit is further configured to:
when the difference between the first number of memory cells between the two adjacent preset read voltages and the first preset number is less than or equal to a first difference threshold, perform the second program operation on the memory cells; and
when the difference between the first number of memory cells between the two adjacent preset read voltages and the first preset number is greater than the first difference threshold, receive the error-corrected data obtained after the error correction of the program result of the first program operation.
5 . The memory of claim 2 , wherein the peripheral circuit is further configured to:
using the plurality of preset read voltages as the default read level, read the second number of memory cells within the preset offset range of the default read level; and
determine the fail bit count based on the second number of memory cells within the preset offset range of the default read level.
6 . The memory of claim 5 , wherein the peripheral circuit is further configured to:
when the second number of memory cells within the preset offset range of the default read level is less than or equal to the second preset number, perform the second program operation on the memory cells; and
when the second number of memory cells within the preset offset range of the default read level is greater than the second preset number, receive the error-corrected data obtained after the error correction of the program result of the first program operation.
7 . The memory of claim 1 , wherein the peripheral circuit is further configured to:
receive first program data from a memory interface, and perform the first program operation on the memory cells according to the first program data to obtain n programmed states, n being a positive integer; and
when the fail bit count read corresponding to the program result meets the preset requirement, receive second program data from the memory interface, and perform the second program operation on the memory cells according to the first program data and the second program data to obtain m programmed states, where n≤m.
8 . The memory of claim 7 , wherein the peripheral circuit is further configured to:
when the fail bit count read corresponding to the program result does not meet the preset requirement, receive the first program data after error correction with memory error correction code (ECC) from the memory interface; and
receive the second program data from the memory interface, and perform the second program operation on the memory cells according to the first program data after the error correction with the ECC and the second program data to obtain the m programmed states.
9 . The memory of claim 1 , wherein the peripheral circuit is further configured to:
determine the first number of memory cells between the two adjacent preset read voltages of the plurality of preset read voltages; and
when the difference in the first number of memory cells between the two adjacent preset read voltages and the first preset number is less than or equal to a first difference threshold, perform the second program operation on the memory cells.
10 . The memory of claim 1 , wherein the peripheral circuit is further configured to:
determine the second number of memory cells within the preset offset range of the default read level; and
when the second number of memory cells within the preset offset range of the default read level is less than or equal to the second preset number, perform the second program operation on the memory cells.
11 . A memory system, comprising:
a memory comprising a memory array that includes memory cells; and
a memory controller configured to send first program data to the memory;
wherein the memory is configured to:
perform a first program operation on the memory cells according to the first program data;
perform a read operation on the memory cells;
determine a program result of the first program operation, corresponding to a fail bit count (FBC) read, by one of:
determining the program result based on a first comparison of a first preset number with a difference in a first number of memory cells between two adjacent preset read voltages of a plurality of preset read voltages, wherein the first comparison, between the first preset number and the difference, determines whether error correction of the program result is performed and error-corrected data is received; or
determining the program result based on a second comparison of a second preset number with a second number of memory cells within a preset offset range of a default read level, the plurality of preset read voltages being configured as the default read level, wherein the second comparison, between the second preset number and the second number, determines whether the error correction of the program result is performed and the error-corrected data is received; and
when the fail bit count read corresponding to the program result meets a preset requirement, send first information to the memory controller;
the memory controller is further configured to receive the first information and send second program data to the memory; and
the memory is further configured to perform a second program operation on the memory cells according to the first program data and the second program data.
12 . The memory system of claim 11 , wherein the memory is further configured to:
perform the read operation on the memory cells through the plurality of preset read voltages; and
read the fail bit count based on the plurality of preset read voltages.
13 . The memory system of claim 12 , wherein the memory is further configured to:
read the first number of memory cells between the two adjacent preset read voltages of the plurality of preset read voltages; and
determine the fail bit count based on the first number of memory cells between the two adjacent preset read voltages.
14 . The memory system of claim 13 , wherein the memory is further configured to:
when the difference between the first number of memory cells between the two adjacent preset read voltages and the first preset number is less than or equal to a first difference threshold, perform the second program operation on the memory cells; and
when the difference between the first number of memory cells between the two adjacent preset read voltages and the first preset number is greater than the first difference threshold, receive the error-corrected data obtained after the error correction of the program result of the first program operation.
15 . The memory system of claim 12 , wherein the memory is further configured to:
using the plurality of preset read voltages as the default read level, read the second number of memory cells within the preset offset range of the default read level; and
determine the fail bit count based on the second number of memory cells within the preset offset range of the default read level.
16 . The memory system of claim 15 , wherein the memory is further configured to:
when the second number of memory cells within the preset offset range of the default read level is less than or equal to the second preset number, perform the second program operation on the memory cells; and
when the second number of memory cells within the preset offset range of the default read level is greater than the second preset number, receive the error-corrected data obtained after the error correction of the program result of the first program operation.
17 . The memory system of claim 11 , wherein:
the memory is further configured to, when the fail bit count read corresponding to the program result does not meet the preset requirement, send the program result of the first program data to the memory controller;
the memory controller is further configured to perform error correction with ECC on the program result, and send the first program data after the error correction with the ECC and the second program data to the memory; and
the memory is further configured to perform the second program operation on the memory cells according to the first program data after the error correction with the ECC and the second program data.
18 . A method of programming a memory, comprising:
performing a first program operation on memory cells;
performing a read operation on the memory cells through a plurality of preset read voltages; and
when a fail bit count read based on a program result of the first program operation that the plurality of preset read voltages meets a preset requirement, performing a second program operation on the memory cells, comprising:
based on a difference in a number of memory cells between two adjacent preset read voltages of the plurality of preset read voltages and a first preset number, determining whether to perform the second program operation on the memory cells, wherein a comparison, between the first preset number and the difference, determines whether error correction of the program result is performed and error-corrected data is received.
19 . The method of claim 18 , further comprising:
when the difference in the number of memory cells between the two adjacent preset read voltages and the first preset number is greater than a first difference threshold, receiving the error-corrected data obtained after the error correction of the program result of the first program operation.
20 . The method of claim 18 , wherein performing the read operation on the memory cells through the plurality of preset read voltages comprises:
using the plurality of preset read voltages as a default read level, reading a number of memory cells within a preset offset range of the default read level.