Cascode amplifier bias circuits
Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.
1. A method for biasing the final stages of a cascode amplifier, including:
(a) providing a cascode amplifier having at least two serially connected transistor stages, each transistor stage having a gate, a drain, and a source, the bottom transistor stage having an input configured to be coupled to an RF input signal to be amplified, and the top transistor stage of the cascode amplifier having an output for providing an amplified RF input signal;
(b) providing a cascode reference circuit having at least two serially connected transistor stages, each transistor having a gate, a drain, and a source, the gates of the bottom two transistor stages of the cascode reference circuit being coupled to the corresponding gates of the bottom two transistor stages of the cascode amplifier, for biasing the cascode amplifier to output a final current approximately equal to a multiple of a mirror current in the cascode reference circuit;
(c) coupling a first current source to the drain of the top transistor stage of the cascode reference circuit;
(d) providing a voltage offset circuit including a resistor series-connected between a first current source and a second current source, the drain of the top transistor stage of the cascode reference circuit being coupled between the resistor and the first current source; and
(e) providing a source follower transistor having a gate, a drain, and a source, the drain of the source follower transistor being coupled to a voltage source, the source of the source follower transistor being coupled to a third current source and to the respective gates of the bottom transistor stages of the cascode reference circuit and the cascode amplifier, and the gate of the source follower transistor being coupled to the voltage offset circuit between the resistor and the second current source, the source follower transistor being responsive to variations in voltage and/or current in the cascode reference circuit to output an adjustment gate bias voltage applied to the respective gates of the bottom transistor stage of the cascode amplifier and of the cascode reference circuit that forces the mirror current in the cascode reference circuit to be approximately equal to a selected current value.
2. The method of claim 1 , wherein the corresponding drain voltages of the bottom transistor stage of the cascode amplifier and the cascode reference circuit are approximately the same.
3. The method of claim 1 , or, wherein the cascode reference circuit is a split cascode reference circuit.
4. The method of claim 1 , further including providing an input impedance matching network coupled to the input of the bottom transistor stage and configured to be coupled to the RF input signal to be amplified.
5. The method of claim 1 , further including providing an output impedance matching network coupled to the output.
6. The method of claim 1 , further including providing a respective decoupling network coupled between corresponding gates of each of the bottom two transistor stages of the cascode amplifier.
7. The method of claim 6 , wherein at least one decoupling network includes a programmable resistance element for varying bias levels to the coupled gates.
8. The method of claim 1 , further including:
(a) coupling a degeneration inductor between the source of the bottom transistor stage of the cascode amplifier and RF ground, the degeneration inductor having a first resistance; and
(b) coupling a compensation resistor between the source of the bottom transistor stage of the cascode reference circuit and RF ground, the compensation resistor having a second resistance such that the voltage at the source of the bottom transistor stage of the cascode reference circuit closely approximates the voltage at the source of the bottom transistor stage of the cascode amplifier.
9. The method of claim 1 , wherein the input to the bottom transistor stage is coupled to the gate of the bottom transistor stage.
10. The method of claim 1 , wherein the input to the bottom transistor stage is coupled to the source of the bottom transistor stage.
11. A method for biasing the final stages of a cascode amplifier, including:
(a) providing a cascode amplifier having at least two serially connected transistor stages, each transistor stage having a gate, a drain, and a source, the bottom transistor stage having an input configured to be coupled to an RF input signal to be amplified, and the top transistor stage of the cascode amplifier having an output for providing an amplified RF input signal;
(b) providing a split cascode reference circuit having at least two transistor stages, each transistor having a gate, a drain, and a source, the gates of the bottom two transistor stages of the cascode reference circuit being coupled to the corresponding gates of the bottom two transistor stages of the cascode amplifier, for biasing the cascode amplifier to output a final current approximately equal to a multiple of a mirror current in the cascode reference circuit, the drain of the bottom transistor stage of the cascode reference circuit being coupled to a first mirror current source and the source of the bottom transistor stage of the cascode reference circuit being coupled to circuit ground, and the drain of the next-to-bottom transistor stage of the cascode reference circuit being coupled to a voltage source and the source of the next-to-bottom transistor stage of the cascode reference circuit being coupled to a second mirror current source; and
(c) providing an op-amp having a first and a second input and an output, the first input being coupled to the source of the next-to-bottom transistor stage of the cascode reference circuit, the second input being coupled to the drain of the bottom transistor stage of the cascode reference circuit, the output being coupled to the respective gates of the bottom transistor stages of the cascode reference circuit and the cascode amplifier, wherein the op-amp is responsive to differences between its first and second inputs and outputs an adjustment gate bias voltage applied to the respective gates of the bottom transistor stage of the cascode amplifier and of the cascode reference circuit that forces the mirror current in the cascode reference circuit to be approximately equal to a selected current value.
12. The method of claim 11 , wherein the corresponding drain voltages of the bottom transistor stage of the cascode amplifier and the cascode reference circuit are approximately the same.
13. The method of claim 11 , wherein the cascode reference circuit is a split cascode reference circuit.
14. The method of claim 11 , further including providing an input impedance matching network coupled to the input of the bottom transistor stage and configured to be coupled to the RF input signal to be amplified.
15. The method of claim 11 , further including providing an output impedance matching network coupled to the output.
16. The method of claim 11 , further including providing a respective decoupling network coupled between corresponding gates of each of the bottom two transistor stages of the cascode amplifier.
17. The method of claim 16 , wherein at least one decoupling network includes a programmable resistance element for varying bias levels to the coupled gates.
18. The method of claim 11 , further including:
(a) coupling a degeneration inductor between the source of the bottom transistor stage of the cascode amplifier and RF ground, the degeneration inductor having a first resistance; and
(b) coupling a compensation resistor between the source of the bottom transistor stage of the cascode reference circuit and RF ground, the compensation resistor having a second resistance such that the voltage at the source of the bottom transistor stage of the cascode reference circuit closely approximates the voltage at the source of the bottom transistor stage of the cascode amplifier.
19. The method of claim 11 , wherein the input to the bottom transistor stage is coupled to the gate of the bottom transistor stage.
20. The method of claim 11 , wherein the input to the bottom transistor stage is coupled to the source of the bottom transistor stage.