Low-power resistor-less voltage reference circuit
A method for generating a reference voltage includes generating a proportional-to-absolute temperature (PTAT) voltage across a first pseudo resistor. The first pseudo resistor includes a transistor. The method also includes converting the PTAT voltage to a current based on a resistance of the first pseudo resistor. The method also includes mirroring the current using a current mirror circuit and converting the mirrored current to a converted PTAT voltage using a second pseudo resistor. The second pseudo resistor includes a transistor. The first pseudo resistor and the second pseudo resistor include equal transistor types. The method also includes generating a complementary-to-absolute temperature (CTAT) voltage, and summing the converted PTAT voltage and the CTAT voltage to produce the reference voltage. The resulting reference voltage is temperature independent.
1. A low power, resistor-less voltage reference circuit, comprising:
a proportional-to-absolute-temperature (PTAT) voltage generator configured to produce a PTAT voltage across a first pseudo resistor, wherein the first pseudo resistor comprises a transistor, wherein the PTAT voltage across the first pseudo resistor produces a current based on a resistance of the first pseudo resistor;
a current mirror circuit configured to mirror the current;
a second pseudo resistor comprising a transistor, wherein the second pseudo resistor is used to convert the mirrored current to a converted PTAT voltage, wherein the first pseudo resistor and the second pseudo resistor comprise equal transistor types; and
a complementary-to-absolute-temperature (CTAT) voltage generator configured to produce a CTAT voltage, wherein the CTAT voltage is summed with the converted PTAT voltage to produce a reference voltage, wherein the reference voltage is temperature independent.
2. The voltage reference circuit of claim 1 , wherein the PTAT voltage generator and the CTAT voltage generator comprise transistors operating in sub-threshold mode.
3. The voltage reference circuit of claim 2 , wherein the current mirror circuit comprises bias pseudo resistors configured to maintain cascode transistors of the current mirror circuit in saturation.
4. The voltage reference circuit of claim 3 , wherein the bias pseudo resistors each comprise a power down input to prevent current flow through the current mirror circuit.
5. The voltage reference circuit of claim 1 , wherein the transistor of the first pseudo resistor comprises a gate-to-substrate voltage and a source-to-substrate voltage equal to corresponding voltage values of the transistor of the second pseudo resistor.
6. The voltage reference circuit of claim 5 , wherein gates for the transistor of the first pseudo resistor and the transistor of the second pseudo resistor are connected to the reference voltage.
7. The voltage reference circuit of claim 1 , wherein the transistor of the first pseudo resistor and the transistor of the second pseudo resistor comprise equal threshold voltages, oxide capacitance, and electron mobility.
8. A method for generating a reference voltage, the method comprising:
generating a proportional-to-absolute temperature (PTAT) voltage across a first pseudo resistor, wherein the first pseudo resistor comprises a transistor;
converting the PTAT voltage to a current based on a resistance of the first pseudo resistor;
mirroring the current using a current mirror circuit;
converting the mirrored current to a converted PTAT voltage using a second pseudo resistor, wherein the second pseudo resistor comprises a transistor, wherein the first pseudo resistor and the second pseudo resistor comprise equal transistor types;
generating a complementary-to-absolute temperature (CTAT) voltage; and
summing the converted PTAT voltage and the CTAT voltage to produce the reference voltage, wherein the reference voltage is temperature independent.
9. The method of claim 8 , wherein the current mirror circuit comprises a cascode current mirror.
10. The method of claim 8 , further comprising self-biasing cascode transistors in the current mirror circuit using bias pseudo resistors to maintain the cascode transistors of the current mirror circuit in saturation.
11. The method of claim 10 , further comprising preventing current flow through the current mirror circuit via a power down input to the bias pseudo resistors.
12. The method of claim 8 , further comprising setting a gate-to-substrate voltage and a source-to-substrate voltage of the transistor of the first pseudo resistor equal to corresponding voltage values of the transistor of the second pseudo resistor.
13. The method of claim 12 , wherein gates for the transistor of the first pseudo resistor and the transistor of the second pseudo resistor are connected to the reference voltage.
14. The method of claim 8 , wherein the transistor of the first pseudo resistor and the transistor of the second pseudo resistor comprise equal threshold voltages, oxide capacitance, and electron mobility.
15. A system, comprising:
an electronic circuit configured to generate an output voltage;
a voltage reference circuit, the voltage reference circuit comprising:
a proportional-to-absolute-temperature (PTAT) voltage generator configured to produce a PTAT voltage across a first pseudo resistor, wherein the first pseudo resistor comprises a transistor, wherein the PTAT voltage across the first pseudo resistor produces a current based on a resistance of the first pseudo resistor;
a current mirror circuit configured to mirror the current;
a second pseudo resistor comprising a transistor, wherein the second pseudo resistor is used to convert the mirrored current to a converted PTAT voltage, wherein the first pseudo resistor and the second pseudo resistor comprise equal transistor types; and
a complementary-to-absolute-temperature (CTAT) voltage generator configured to produce a CTAT voltage, wherein the CTAT voltage is summed with the converted PTAT voltage to produce a reference voltage, wherein the reference voltage is temperature independent; and
a comparator configured to compare the output voltage of the electronic circuit to the reference voltage.
16. The system of claim 15 , wherein the current mirror circuit comprises a cascode current mirror, wherein the cascode current mirror comprises bias pseudo resistors configured to maintain the cascode transistors of the current mirror circuit in saturation.
17. The system of claim 16 , wherein the bias pseudo resistors each comprise a power down input to prevent current flow through the current mirror circuit.
18. The system of claim 15 , wherein the transistor of the first pseudo resistor comprises a gate-to-substrate voltage and a source-to-substrate voltage equal to corresponding voltage values of the transistor of the second pseudo resistor.
19. The system of claim 18 , wherein gates for the transistor of the first pseudo resistor and the transistor of the second pseudo resistor are connected to the reference voltage.
20. The system of claim 15 , wherein the transistor of the first pseudo resistor and the transistor of the second pseudo resistor comprise equal threshold voltages, oxide capacitance, and electron mobility.