Dual path clock forwarding
Retimers and retiming methods may employ dual path clock forwarding to drive a transmit clock generator. One illustrative integrate retimer circuit includes: a sampling element configured to produce a digital receive signal by sampling an analog receive signal in accordance with a sampling signal; a timing error estimator configured to produce a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal; a clock recovery circuit configured to derive the sampling signal from the estimated timing error and a reference clock in part by determining a frequency signal; a transmitter configured to retransmit the digital receive signal in accordance with a transmit clock; and a transmit clock generator configured to derive the transmit clock. The transmit clock generator operates based on each of: the reference clock; the frequency signal; and a phase error of the transmit clock relative to the sampling signal.
1 . An integrated retimer circuit that comprises:
a sampling element configured to produce a digital receive signal by sampling an analog receive signal in accordance with a sampling signal;
a timing error estimator configured to produce a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal;
a clock recovery circuit configured to derive the sampling signal from the estimated timing error and a reference clock in part by determining a frequency signal;
a transmitter configured to retransmit the digital receive signal in accordance with a transmit clock; and
a transmit clock generator configured to derive the transmit clock based on each of:
the reference clock;
the frequency signal; and
a phase error of the transmit clock relative to the sampling signal,
wherein the transmit clock generator includes a clock forwarding filter having:
a phase comparator to determine the phase error;
a phase filter coupled to the phase comparator to derive a filtered phase error; and
a frequency filter to derive a filtered frequency signal.
2 . The integrated retimer circuit of claim 1 , wherein the frequency signal is a division ratio for a fractional-N phase lock loop in a clock signal path for deriving the sampling signal from the reference clock, and wherein the transmit clock generator includes a fractional-N phase lock loop in a clock signal path for deriving the transmit clock from the reference clock.
3 . The integrated retimer circuit of claim 1 , wherein the frequency signal is a frequency offset for a phase interpolator in a clock signal path for deriving the sampling signal from the reference clock, and wherein the transmit clock generator includes a phase interpolator in a clock signal path for deriving the transmit clock from the reference clock.
4 . The integrated retimer circuit of claim 3 , wherein the clock signal path for deriving the sampling signal includes a fractional-N phase lock loop configured to receive a division ratio from the clock recovery circuit, and wherein the transmit clock generator includes division ratio filter configured to provide a filtered division ratio to a fractional-N phase lock loop in the clock signal path for deriving the transmit clock.
5 . The integrated retimer circuit of claim 1 , wherein the phase filter includes a jitter filter.
6 . The integrated retimer circuit of claim 5 , wherein the phase filter is a second-order filter.
7 . The integrated retimer circuit of claim 1 , wherein the phase error is based on a difference between a write pointer for a buffer and a read pointer for the buffer.
8 . The integrated retimer circuit of claim 1 , further comprising a secondary clock forwarding filter that aligns a secondary transmit clock to said transmit clock.
9 . A retiming method that comprises:
sampling an analog receive signal in accordance with a sampling signal to obtain a digital receive signal;
producing a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal;
deriving the sampling signal from the estimated timing error and a reference clock in part by determining a frequency signal;
retransmitting the digital receive signal in accordance with a transmit clock; and
using a transmit clock generator to derive the transmit clock based on each of: the reference clock, the frequency signal, and a phase error of the transmit clock relative to the sampling signal, the transmit clock generator including a clock forwarding filter having:
a phase comparator to determine the phase error;
a phase filter coupled to the phase comparator to derive a filtered phase error; and
a frequency filter to derive a filtered frequency signal.
10 . The retiming method of claim 9 , wherein the frequency signal is a division ratio for a fractional-N phase lock loop in a clock signal path for deriving the sampling signal from the reference clock, and wherein the transmit clock generator includes a fractional-N phase lock loop in a clock signal path for deriving the transmit clock from the reference clock.
11 . The retiming method of claim 9 , wherein the frequency signal is a frequency offset for a phase interpolator in a clock signal path for deriving the sampling signal from the reference clock, and wherein the transmit clock generator includes a phase interpolator in a clock signal path for deriving the transmit clock from the reference clock.
12 . The retiming method of claim 9 , wherein the phase filter includes a jitter filter.
13 . The retiming method of claim 12 , wherein the phase filter is a second-order filter.
14 . The retiming method of claim 9 , wherein the phase error is based on a difference between a write address pointer for a buffer and a read address pointer for the buffer.