Dynamic eye opening monitor
A method for identifying margins in an eye opening includes capturing first data from a data signal based on edges in a data clock signal, capturing second data from the data signal responsive to edges in a phase shifted version of the data clock signal, iteratively increasing phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially matches the second data until the first data differs from the second data, iteratively decreasing the phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially differs from the second data until the first data matches the second data, and determining the margin of the eye opening when the first data begins to match the second data or when the first data begins to differ from the second data.
1 . An eye opening monitor, comprising:
a first sampling circuit configured to capture first data from a data signal responsive to edges in a data clock signal;
a second sampling circuit configured to capture second data from the data signal responsive to edges in a phase shifted version of the data clock signal; and
a processing circuit configured to determine a margin of an eye opening by:
iteratively increasing a phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially matches the second data until the first data differs from the second data; or
iteratively decreasing the phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially differs from the second data until the first data matches the second data,
wherein a phase shift between a receive clock signal and the data clock signal remains unchanged while the processing circuit determines the margin of the eye opening.
2 . The eye opening monitor of claim 1 , wherein the phase shifted version of the data clock signal is initially a quadrature version of the data clock signal.
3 . The eye opening monitor of claim 1 , wherein the eye opening monitor is included in a serial interface, and wherein the processing circuit is further configured to determine the margin of the eye opening while the serial interface is transferring data during a normal mode of operation.
4 . The eye opening monitor of claim 3 , wherein the eye opening monitor is enabled periodically during the normal mode of operation and wherein the processing circuit is further configured to modify the phase shift between the receive clock signal and the data clock signal when a change in location of the margin of the eye opening is detected.
5 . The eye opening monitor of claim 3 , wherein the eye opening monitor is enabled when an error is detected in the data transferred during the normal mode of operation.
6 . The eye opening monitor of claim 1 , further comprising:
a first phase control circuit that is configured to generate the data clock signal; and
a second phase control circuit that responds to an output of the first phase control circuit and that is configured to control the phase difference between the phase shifted version of the data clock signal and the data clock signal.
7 . The eye opening monitor of claim 6 , wherein the second phase control circuit is configured independently of the first phase control circuit.
8 . An apparatus, comprising:
means for capturing data from a data signal to provide first data captured based on edges in a data clock signal and second data captured based on edges in a phase shifted version of the data clock signal;
means for modifying phase difference between the phase shifted version of the data clock signal and the data clock signal; and
a controller configured to:
cause the means for modifying phase difference to iteratively increase the phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially matches the second data until the first data differs from the second data;
cause the means for modifying phase difference to iteratively decrease the phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially differs from the second data until the first data matches the second data; and
determine a margin of an eye opening when the first data begins to match the second data or when the first data begins to differ from the second data,
wherein a phase shift between a receive clock signal and the data clock signal remains unchanged until the margin of the eye opening is determined.
9 . The apparatus of claim 8 , wherein the phase shifted version of the data clock signal is initially a quadrature version of the data clock signal.
10 . The apparatus of claim 8 , wherein the apparatus is included in a serial interface, and wherein the controller is further configured to determine the margin of the eye opening while the serial interface is transferring data during a normal mode of operation.
11 . The apparatus of claim 10 , wherein the means for modifying phase difference is enabled periodically during the normal mode of operation and wherein the controller is further configured to modify the phase shift between the receive clock signal and the data clock signal when a change in location of the margin of the eye opening is detected.
12 . The apparatus of claim 10 , wherein the means for modifying phase difference is enabled when an error is detected in the data transferred during the normal mode of operation.
13 . The apparatus of claim 8 , further comprising:
a first phase control circuit that is configured to generate the data clock signal; and
a second phase control circuit that responds to an output of the first phase control circuit and that is configured to control the phase difference between the phase shifted version of the data clock signal and the data clock signal, wherein the second phase control circuit is configured independently of the first phase control circuit.
14 . A method for identifying margins in an eye opening, comprising:
capturing first data from a data signal based on edges in a data clock signal;
capturing second data from the data signal responsive to edges in a phase shifted version of the data clock signal;
iteratively increasing a phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially matches the second data until the first data differs from the second data; and
iteratively decreasing the phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially differs from the second data until the first data matches the second data,
determining a margin of the eye opening when the first data begins to match the second data or when the first data begins to differ from the second data, wherein a phase shift between a receive clock signal and the data clock signal remains unchanged until the margin of the eye opening is determined.
15 . The method of claim 14 , wherein the phase shifted version of the data clock signal is initially a quadrature version of the data clock signal.
16 . The method of claim 14 , wherein the eye opening monitor is included in a serial interface, and wherein the margin of the eye opening is determined while the serial interface is transferring data during a normal mode of operation.
17 . The method of claim 16 , further comprising:
periodically enabling the eye opening monitor during the normal mode of operation; and
modifying the phase shift between the receive clock signal and the data clock signal when a change in location of the margin of the eye opening is detected.
18 . The method of claim 16 , wherein the eye opening monitor is enabled when an error is detected in the data transferred during the normal mode of operation.
19 . The method of claim 14 , further comprising:
generating the data clock signal using a first phase control circuit; and
controlling the phase difference between the phase shifted version of the data clock signal and the data clock signal using a second phase control circuit that responds to an output of the first phase control circuit.
20 . The method of claim 19 , wherein the second phase control circuit is configured independently of the first phase control circuit.