Signal recovery circuit
A signal recovery circuit capable of expanding the receive margin is provided. The signal recovery circuit comprises for example a clock generator unit CLK_GEN for generating the clock signals CLKa, CLKb, and CLKc, a window width control unit WW_CTL, and a clock data discriminator unit CD_JGE for generating a phase detector signal (EARLY, LATE) when for example a data signal Di pulse edge enters between the CLKa and CLKb, or between the CLKb and CLKc, and the clock generator unit. Along with exerting control based on these phase detection signals to maintain the mutual phase differential of the overall phase of CLKa, CLKb, CLKc so as to prevent intrusion of the above described Di edge, the CLK_GEN also regulates the phase differential between CLKa and CLKb, and the phase differential between CLKb and CLKc based on a signal (Sww) from the WW_CTL.
1. A signal recovery circuit comprising:
a clock generator unit to generate a first clock edge, and a second clock edge different from the first clock edge;
a phase comparator unit to judge if the edge of the data signal that was input has entered into a first window which is the period between the first clock edge and the second clock edge, and to output a phase detection signal if the data signal edge has entered into the first window; and
a window width control unit to output a window width control signal, wherein the clock generator unit includes:
a first unit to control the phase of the first clock edge and the second clock edge according to the phase detection signal, while still maintaining the width of the first window so that the data signal edge does not enter within the first window; and
a second unit to control the width of the first window according to the window width control signal.
2. The signal recovery circuit according to claim 1 , wherein the window width control unit includes:
a frequency calculator circuit to calculate the frequency of occurrence of the phase detection signal, and
a first circuit to generate the window width control signal so that the frequency of occurrence of the phase detection signals converges on the preset optimal value.
3. The signal recovery circuit according to claim 1 , wherein the window width control unit includes a first table to define the interrelation between the first window width, and the length of a transmission path forming input source for the data signal.
4. The signal recovery circuit according to claim 3 , wherein the window width control unit further includes a first measurement circuit to measure the length of the transmission path.
5. The signal recovery circuit according to claim 4 , wherein the window width control unit includes:
a second measurement circuit to measure the bit error rate of the data signal that was input, and a first circuit to generate the window width control signal to make the bit error rate of the data signal lower than a preset reference value.
6. The signal recovery circuit according to claim 5 , wherein, the window width control unit operates during the training period.
7. The signal recovery circuit according to claim 5 , wherein the window width control unit includes a third measurement circuit to measure the aperture width of the eye for the receive data that was input, and generates the window width control signal according to those measurement results.
8. The signal recovery circuit according to claim 7 , wherein the window width control unit operates during the training period.
9. A signal recovery circuit comprising:
a clock generator unit to generate a first clock edge, a second clock edge whose phase is earlier than the first clock edge, and a third clock edge whose phase is delayed more than the first clock edge;
a phase comparator unit to judge if the edge of the data signal that was input has entered within a first window which is the period between the first clock edge and the second clock edge, and output a first phase detection signal if the data signal edge has entered within the first window; and
further to judge if the edge of the data signal has entered within a second window which is the period between the first clock edge and the third clock edge, and output a second phase detection signal if the data signal edge has entered within the second window; and
a window width control unit to output a first window width control signal and a second window width control signal,
wherein the clock generator unit includes:
a first unit to control the phase of the first, the second and the third clock edge while maintaining the width of the first and the second window according to the first phase detection signal so that the edge of the data signal does not enter within the first window; and
to control the phase of the first, the second and the third clock edge while maintaining the first and the second window width according to the second phase detection signal so that the edge of the data signal does not enter within the second window; and
a second unit to control the first window width according to the first window width control signal and to control the second window width according to the second window width control signal.
10. The signal recovery circuit according to claim 9 , wherein the window width control unit includes:
a first frequency calculator circuit to calculate the frequency of occurrence of the first phase detection signal, a second frequency calculator circuit to calculate the frequency of occurrence of the second phase detection signal, a first circuit to generate the first window width control signal so that the frequency of occurrence of the first phase detection signal is within a preset first range, and a second circuit to generate the second window width control signal so that the frequency of occurrence of the second phase detection signal is within a preset second range.
11. The signal recovery circuit according to claim 10 , which, includes a window width control unit, further comprising:
a first measurement circuit to measure the aperture width of the eye of the receive data that was input, a third circuit to set the first clock edge in the vicinity of the aperture width of the eye measured by the first measurement circuit,
wherein the first and the second frequency calculation circuits, and the first and the second circuits operate with the first clock edge position set by the third circuit as the initial state.
12. The signal recovery circuit according to claim 10 , wherein the window width control unit includes:
a third frequency calculator circuit to calculate the total frequency of occurrences of the first phase detection signal and the second phase detection signal, and a third circuit to generate the first and the second window width control signal to make the first window width and the second window width equal so that the total frequency of occurrences is within a preset third range.