Strongarm comparator and asynchronous SAR ADC
Provided are a StrongArm comparator and an SAR ADC. The StrongArm comparator includes an input module, a latch module, a first reset unit and a shunt unit. The input module is configured to receive a pair of differential input voltages, and the latch module is configured to generate a pair of differential output voltages. Operation of the first reset unit is controlled by a first clock signal, discharging of the coupling nodes of the input and latch modules through the input module is activated by an active pulse of the first clock signal, and discharging of the coupling nodes through the shunt unit is activated by an active pulse of a second clock signal, where a leading edge of the active pulse of the second clock signal lags behind the active pulse of the first clock signal, and trailing edges of the first and second clock signals end simultaneously.
1 . A StrongArm comparator, comprising:
an input module, configured to receive a pair of differential input voltages;
a latch module, coupled between a first supply and the input module, and configured to generate a pair of differential output voltages; and
a reset module, comprising a first reset unit and a shunt unit, wherein the first reset unit is coupled between the first supply and internal nodes of the StrongArm comparator, and operation of the first reset unit is controlled by a first clock signal, wherein the shunt unit is coupled between a second supply and coupling nodes of the input module and the latch module,
wherein discharging of the coupling nodes through the input module for triggering generation of the pair of differential output voltages is activated by an active pulse of the first clock signal, and discharging of the coupling nodes through the shunt unit is activated by an active pulse of a second clock signal, wherein a leading edge of the active pulse of the second clock signal lags behind a leading edge of the active pulse of the first clock signal, and trailing edges of the first clock signal and the second clock signal end simultaneously.
2 . The StrongArm comparator according to claim 1 , wherein:
the input module comprises a pair of first transistors, the pair of first transistors is configured to respectively receive the pair of differential input voltages on gates of the first transistors, and sources of the first transistors are coupled to a drain of a second transistor having a source being coupled to the second supply and a gate being configured to receive the first clock signal; and
the shunt unit comprises a pair of third transistors, each of the third transistors is coupled between a drain of a corresponding first transistor and the second supply, and gates of the third transistors are configured to receive the second clock signal.
3 . An asynchronous successive approximation register (SAR) analog-to-digital converter (ADC), configured to convert an analog input signal into digital output signals and comprising: a StrongArm comparator, a capacitive digital to analog converter (CDAC) and a control module;
wherein the StrongArm comparator comprises:
an input module, configured to receive a pair of differential input voltages,
a latch module, coupled between a first supply and the input module, and configured to generate a pair of differential output voltages, and
a reset module, comprising a first reset unit and a shunt unit, wherein the first reset unit is coupled between the first supply and internal nodes of the StrongArm comparator, and operation of the first reset unit is controlled by a first clock signal, wherein the shunt unit is coupled between a second supply and coupling nodes of the input module and the latch module,
wherein discharging of the coupling nodes through the input module for triggering generation of the pair of differential output voltages is activated by an active pulse of the first clock signal, and discharging of the coupling nodes through the shunt unit is activated by an active pulse of a second clock signal, wherein a leading edge of the active pulse of the second clock signal lags behind a leading edge of the active pulse of the first clock signal, and trailing edges of the first clock signal and the second clock signal end simultaneously;
wherein differential outputs of the CDAC are coupled to the input module of the StrongArm comparator, inputs of the CDAC are coupled to outputs of the control module, outputs of the StrongArm comparator are coupled to inputs of the control module;
the CDAC is configured to generate a succession of two differential input voltages at the input module of the StrongArm comparator to successively approximate a sampled differential voltage acquired from differential analog input ends during an active pulse of a sampling signal;
wherein generation of the succession of the two differential input voltages is based on successive approximation logic signals from the control module;
the StrongArm comparator is configured to generate, based on the first clock signal from the control module, a comparison signal representing a comparison result between the two differential input voltages, wherein the comparison result indicates a bit value of the digital output signals to be stored in the control module; and
the control module is configured to detect the comparison signal, generate the first clock signal for the StrongArm comparator based on detection of the comparison signal, the sampling signal and a first reset signal for resetting the StrongArm comparator, output the successive approximation logic signals to the CDAC based on the comparison signal, and output the digital output signals after all bit values of the digital output signals are converted.
4 . The SAR ADC according to claim 3 , wherein:
the input module comprises a pair of first transistors, the pair of first transistors is configured to respectively receive the pair of differential input voltages through gates of the first transistors, and sources of the first transistors are coupled to a drain of a second transistor having a source being coupled to the second supply and a gate being configured to receive the first clock signal; and
the shunt unit comprises a pair of third transistors, each of the third transistors is coupled between a drain of a corresponding first transistor and the second supply, and gates of the third transistors are configured to receive the second clock signal.
5 . The SAR ADC according to claim 3 , wherein the discharging of the coupling nodes through the shunt unit is activated during conversion of a last bit of the digital output signals.
6 . The SAR ADC according to claim 3 , wherein an active pulse of the first reset signal is inside the active pulse of the sampling signal for sampling the analog input signal.
7 . The SAR ADC according to claim 3 , further comprising two input switches coupled between the differential analog input ends and the input module of the StrongArm comparator, and controlled to be conductive by the active pulse of the sampling signal; and a CDAC reset switch coupled between the input module of the StrongArm comparator and controlled to be conductive by an active pulse of a second reset signal.
8 . The SAR ADC according to claim 7 , wherein the second reset signal is configured to reset the control module and the CDAC, and a leading edge of the active pulse of the second reset signal is triggered by the leading edge of the active pulse of the first clock signal during conversion of a last bit of the digital output signals.