Asynchronous SAR ADC with detection and correction circuit for large amplitude output code errors
An N-bit successive SAR includes, in part, a differential comparator receiving a pair of differential input signals and generating a pair of differential comparator output signals; an N-bit register storing the comparator output signals; a capacitive DAC supplying differential feedback signals to the differential comparator in response to the register; and M detection circuits each associated with one of M most significant bits of the N-bit register. Each detection circuit includes: a PMOS transistor precharging a first node to a supply voltage; a first NMOS transistor having a drain coupled to the first node, and a gate receiving a first voltage representative of one of the differential feedback signals; a second NMOS transistor having a drain coupled to a source of the first NMOS transistor, a gate receiving a second voltage representative of the other one of the differential feedback signals, and a source coupled to a ground terminal.
1 . An N-bit successive approximation register (SAR) configured to convert an analog signal to a digital signal, the SAR comprising:
a differential comparator adapted to receive a pair of differential input signals and generate a pair of differential comparator output signals;
an N-bit register adapted to store the differential comparator output signals;
a capacitive digital-to-analog converter (DAC) adapted to supply a pair of differential feedback signals to the differential comparator in response to the signals stored in the N-bit register; and
M detection circuits each associated with a different one of M most significant bits of the N-bit register, each detection circuit comprising:
a PMOS transistor adapted to precharge a first node to a supply voltage;
a first NMOS transistor having a drain terminal coupled to the first node, and a gate terminal adapted to receive a first voltage representative of a first one of the pair of differential feedback signals;
a second NMOS transistor having a drain terminal coupled to a source terminal of the first NMOS transistor, a gate terminal adapted to receive a second voltage representative of a second one of the pair of differential feedback signals, and a source terminal coupled to a ground terminal; and a latch coupled to the first node and adapted to store the first node's voltage after the first and second voltages are applied respectively to the gate terminals of the first and second NMOS transistors, wherein N is an integer greater than 1 and M is an integer equal to or smaller than N.
2 . The SAR of claim 1 further comprising:
a correction circuit configured to set bit N of an output of the SAR to a logic 1, and set the remaining (N−1) output bits of the SAR to logic 0 if a signal representative of an output of the latch associated with bit N is set to a first logic state.
3 . The SAR of claim 2 wherein the correction circuit is further configured to set bit (N−1) of the output of the SAR to a logic 1, and set the remaining (N−2) output bits of the SAR to logic 0 if the signal representative of an output of the latch associated with bit (N−1) is set to the first logic state.
4 . The SAR of claim 3 wherein the correction circuit is further configured to set bit (N−2) of the output of the SAR to a logic 1, and set the remaining (N−3) output bits of the SAR to logic 0 if the signal representative of an output of the latch associated with bit (N−2) is set to the first logic state.
5 . The SAR of claim 4 further comprising:
a signal sampler adapted to supply the pair of differential input signals in response to a pair of received differential signals.
6 . The SAR of claim 5 wherein the differential comparator comprises:
a first chain of inverters adapted to supply a first one of the pair of differential comparator output signals; and
a second chain of inverters adapted to supply a second one of the pair of differential comparator output signals.
7 . The SAR of claim 6 further comprising:
one or more inverters coupled to an output of the latch associated with each of the M most significant bits of the N-bit register.
8 . A method of detecting an error in an N-bit successive approximation register (SAR) configured to convert an analog signal to a digital signal, the method comprising:
generating a pair of differential output signals in response to comparing a pair of differential input signals received by a comparator during each of N conversion cycles;
storing the N pairs of differential output signals in an N-bit register;
supplying a pair of differential feedback signals, defined by the signals stored in the N-bit register, to the comparator during each of the N conversion cycles; and
for each of M most significant bits of the N-bit register,
precharging a first node to a supply voltage using a PMOS transistor;
applying a first voltage representative of a first one of the pair of differential feedback signals to a gate terminal of a first NMOS transistor having a drain terminal coupled to the first node;
applying a second voltage representative of a second one of the pair of differential feedback signals to a gate terminal of a second NMOS transistor having a drain terminal coupled to a source terminal of the first NMOS transistor, and a source terminal coupled to a ground terminal; and
latching a voltage of the first node, wherein the latched voltage represents an error if the latched voltage is at a first logic state, and wherein N is an integer greater than 1 and M is an integer equal to or smaller than N.
9 . The method of claim 8 further comprising:
setting bit N of an output of the SAR to a logic 1, and setting the remaining (N−1) output bits of the SAR to logic 0 if the latched voltage associated with bit N is at the first logic state.
10 . The method of claim 9 further comprising:
setting bit (N−1) of the output of the SAR to a logic 1, and setting the remaining (N−2) output bits of the SAR to logic 0, if the latched voltage associated with bit (N−1) is at the first logic state.
11 . The method of claim 10 further comprising:
setting bit (N−2) of the output of the SAR to a logic 1, and setting the remaining (N−3) output bits of the SAR to logic 0 if the latched voltage associated with bit (N−2) is at the first logic state.
12 . The method of claim 11 further comprising:
supplying the pair of differential input signals in response to sampling a pair of received differential signals.
13 . The method of claim 12 further comprising:
supplying a first one of the pair of differential output signals via a first chain of inverter; and
supplying a second one of the pair of differential output signals via a second chain of inverter.
14 . The method of claim 13 further comprising:
applying the latched output voltage associated with each of the M most significant bits to one or more inverters.
15 . A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to generate data representative of an N-bit successive approximation register (SAR) configured to convert an analog signal to a digital signal, the SAR comprising:
a differential comparator adapted to receive a pair of differential input signals and generate a pair of differential comparator output signals;
an N-bit register adapted to store the differential comparator output signals;
a capacitive DAC adapted to supply a pair of differential feedback signals to the differential comparator in response to the signals stored in the N-bit register; and
M detection circuits each associated with a different one of M most significant bits of the N-bit register, each detection circuit comprising:
a PMOS transistor adapted to precharge a first node to a supply voltage;
a first NMOS transistor having a drain terminal coupled to the first node, and a gate terminal adapted to receive a first voltage representative of a first one of the pair of differential feedback signals;
a second NMOS transistor having a drain terminal coupled to a source terminal of the first NMOS transistor, a gate terminal adapted to receive a second voltage representative of a second one of the pair of differential feedback signals; and a source terminal coupled to a ground terminal; and
a latch coupled to the first node and adapted to store the first node's voltage after the first and second voltages are applied respectively to the gate terminals of the first and second NMOS transistors, wherein N is an integer greater than 1 and M is an integer equal to or smaller than N.
16 . The non-transitory computer readable medium of claim 15 , wherein the instructions further cause the processor to generate data representative of:
a correction circuit configured to set bit N of an output of the SAR to a logic 1, and set the remaining (N−1) output bits of the SAR to logic 0 if a signal representative of an output of the latch associated with bit N is set to a first logic state.
17 . The non-transitory computer readable medium of claim 16 , wherein the correction circuit is further configured to set bit (N−1) of the output of the SAR to a logic 1, and set the remaining (N−2) output bits of the SAR to logic 0 if the signal representative of an output of the latch associated with bit (N−1) is set to the first logic state.
18 . The non-transitory computer readable medium of claim 17 , wherein the correction circuit is further configured to set bit (N−2) of the output of the SAR to a logic 1, and set the remaining (N−3) output bits of the SAR to logic 0 if the signal representative of an output of the latch associated with bit (N−2) is set to the first logic state.
19 . The non-transitory computer readable medium of claim 18 , wherein the instructions further cause the processor to generate data representative of:
a signal sampler adapted to supply the pair of differential input signals in response to a pair of received differential signals.
20 . The non-transitory computer readable medium of claim 19 , wherein the instructions further cause the processor to generate data representative of:
a first chain of inverters adapted to supply a first one of the pair of differential comparator output signals; and
a second chain of inverters adapted to supply a second one of the pair of differential comparator output signals.