Method and apparatus for simultaneous propagation of multiple clockfrequencies in serializer/deserializer (SerDes) Macros
The disclosed systems, structures, and methods are directed to a two wire-based clock multiplication unit (CMU), employing a first phase lock loop (PLL) configured to generate a first high-speed clock frequency f 1 encoded in differential mode, a second PLL configured to generate a second high-speed clock frequency f 2 encoded in common mode, and a summer configured to combine the differential mode encoding the first high-speed clock frequency f 1 and the common mode encoding the second high-speed clock frequency f 2 and transmit the combined differential and common mode high-speed clock frequencies on a two wire-based conductor bus. In addition, systems, structures, and methods directed to a two wire-based clock recovery module and a two wire-based clock recovery module have also been disclosed.
1. A two wire-based clock multiplication unit (CMU) comprising:
a first phase lock loop (PLL) configured to generate a first high-speed clock frequency f 1 encoded in differential mode;
a second PLL configured to generate a second high-speed clock frequency f 2 encoded in common mode; and
a summer configured to combine the differential mode encoding the first high-speed clock frequency f 1 and the common mode encoding the second high-speed clock frequency f 2 and simultaneously transmit the combined differential and common mode high-speed clock frequencies on a two wire-based conductor bus.
2. The two wire-based CMU of claim 1 , further comprising a first driver and a second driver.
3. The two wire-based CMU of claim 2 , wherein the first driver outputs an in-phase component and an out of phase component associated with the first differential mode encoded high-speed clock frequency f 1 .
4. The two wire-based CMU of claim 3 , wherein the second driver outputs a common mode component associated with the second common mode encoded high-speed clock frequency f 2 .
5. The two wire-based CMU of claim 4 , wherein the summer combines the in-phase component associated with the first differential mode encoded high-speed clock frequency f 1 and common mode component associated with the second common mode encoded high-speed clock frequency f 2 and outputs a first combined component.
6. The two wire-based CMU of claim 5 , wherein the summer transmits the first combined component on a first wire of the two wire-based conductor bus.
7. The two wire-based CMU of claim 4 , wherein the summer combines the out of phase component associated with the first differential mode encoded high-speed clock frequency f 1 and common mode component associated with the second common mode encoded high-speed clock frequency f 2 and outputs a second combined component.
8. The two wire-based CMU of claim 7 , wherein the summer transmits the second combined component on a second wire of the two wire-based conductor bus.
9. A two wire-based clock recovery module comprising:
a common mode rejection pre-filter configured to receive a first combined component from a first wire of a two wire-based conductor bus and receive a second combined component from a second wire of the two wire-based conductor bus, wherein:
the first combined component contains an in-phase component associated with a first high-speed clock frequency f 1 encoded in a differential mode and a common mode component associated with a second high-speed clock frequency f 2 encoded in a common mode,
the second combined component contains an out of phase component associated with the first differential mode encoded high-speed clock frequency f 1 and the common mode component associated with the second common mode encoded high-speed clock frequency f 2 ,
the common mode rejection pre-filter configured to suppress the common mode components in the first and second combined component associated with the second common mode encoded high-speed clock frequency f 2 and outputs the differential mode components associated with the first differential mode encoded high-speed clock frequency f 1 ;
a differential mode rejection pre-filter configured to receive the first combined component and the second combined component, in which the differential mode rejection pre-filter is configured to suppress the in-phase and out of phase components in the first and second combined component associated with the first differential mode encoded high-speed clock frequency f 1 and outputs the common mode component associated with the second common mode encoded high-speed clock frequency f 2 ;
a differential amplifier configured to amplify the differential mode components associated with the first differential mode encoded high-speed clock frequency f 1 and outputs an amplified in-phase and out of phase component associated with the first differential mode encoded high-speed clock frequency f 1 ;
a common mode amplifier configured to amplify the common mode component associated with the second common mode encoded high-speed clock frequency f 2 ; and
an amplifier enabler unit configured to select either the differential amplifier or the common mode amplifier to perform the amplification operation.
10. The two wire-based clock recovery module of claim 9 , wherein the common mode component associated with the second common mode encoded high-speed clock frequency f 2 is converted to an amplified differential mode component.
11. The two wire-based clock recovery module of claim 9 provides either the amplified differential mode components associated with the first differential mode encoded high-speed clock frequency f 1 or the differential mode component associated with the second common mode encoded high-speed clock frequency f 2 to a plurality of transceivers.
12. A two wire-based clock amplification module comprising:
a common mode rejection pre-filter configured to receive a first combined component from a first wire of a two wire-based conductor bus and receive a second combined component from a second wire of the two wire-based conductor bus, wherein:
the first combined component contains an in-phase component associated with a first high-speed clock frequency f 1 encoded in a differential mode and a common mode component associated with a second high-speed clock frequency f 2 encoded in a common mode,
the second combined component contains an out of phase component associated with the first differential mode encoded high-speed clock frequency f 1 and the common mode component associated with the second common mode encoded high-speed clock frequency f 2 , and
the common mode rejection pre-filter configured to suppress the common mode components in the first and second combined component associated with the second common mode encoded high-speed clock frequency f 2 and outputs the differential mode components associated with the first differential mode encoded high-speed clock frequency f 1 ;
a differential mode rejection pre-filter configured to receive the first combined component and the second combined component, in which the differential mode rejection pre-filter is configured to suppress the in-phase and out of phase components in the first and second combined component associated with the first differential mode encoded high-speed clock frequency f 1 and outputs the common mode components associated with the second common mode encoded high-speed clock frequency f 2 ;
a differential amplifier configured to amplify the differential mode component associated with the first differential mode encoded high-speed clock frequency f 1 and outputs an amplified in-phase and out of phase component associated with the first differential mode encoded high-speed clock frequency f 1 ;
a common mode amplifier configured to amplify the common mode component associated with the second common mode encoded high-speed clock frequency f 2 ;
a first summer configured to combine the amplified in-phase component associated with the first differential mode encoded high-speed clock frequency f 1 with the amplified common mode component associated with the second common mode encoded high-speed clock frequency f 2 and outputs a first amplified combined component; and
a second summer configured to combine the amplified out of phase component associated with the first differential mode encoded high-speed clock frequency f 1 with the amplified common mode component associated with the second common mode encoded high-speed clock frequency f 2 and outputs a second amplified combined component.
13. The two wire-based clock amplification module of claim 12 , wherein the first summer transmits the first amplified combined component on the first wire of the two wire-based conductor bus.
14. The two wire-based clock amplification module of claim 12 , wherein the second summer transmits the second amplified combined component on the second wire of the two wire-based conductor bus.
15. A two wire-based clock multiplication unit (CMU) based method of generating and transmitting high-speed clock frequencies comprising:
generating a first high-speed clock frequency f 1 encoded in differential mode;
generating a second high-speed clock frequency f 2 encoded in common mode;
combining the differential mode encoded first high-speed clock frequency f 1 and common mode encoded second high-speed clock frequency f 2 ;
transmitting the combined high-speed clock frequencies on a two wire-based conductor bus.
16. The method of claim 15 , wherein an in-phase component and an out of phase component associated with the first differential mode encoded high-speed clock frequency f 1 is computed.
17. The method of claim 16 , wherein a common mode component associated with the second common mode encoded high-speed clock frequency f 2 is computed.
18. The method of claim 17 , wherein the in-phase component associated with the first differential mode encoded high-speed clock frequency f 1 and common mode component associated with the second common mode encoded high-speed clock frequency f 2 are combined, resulting in a first combined component.
19. The method of claim 18 , wherein the first combined component is transmitted on a first wire of the two wire-based conductor bus.
20. The method of claim 18 , wherein the out of phase component associated with the first differential mode encoded high-speed clock frequency f 1 and common mode component associated with the second common mode encoded high-speed clock frequency f 2 are combined, resulting in a second combined component.
21. The method of claim 20 , wherein the second combined component is transmitted on a second wire of the two wire-based conductor bus.
22. A two wire-based method of clock recovery comprising:
receiving a first combined component from a first wire of a two wire-based conductor bus and receiving a second combined component from a second wire of the two wire-based conductor bus, wherein:
the first combined component contains an in-phase component associated with a first high-speed clock frequency f 1 encoded in a differential mode and a common mode component associated with a second high-speed clock frequency f 2 encoded in a common mode,
the second combined component contains an out of phase component associated with the first differential mode encoded high-speed clock frequency f 1 and the common mode component associated with the second common mode encoded high-speed clock frequency f 2 ;
suppressing the common mode components in the first and second combined component associated with the second common mode encoded high-speed clock frequency f 2 and providing the differential mode components associated with the first differential mode encoded high-speed clock frequency f 1 ;
suppressing the in-phase and out of phase components in the first and second combined component associated with the first differential mode encoded high-speed clock frequency f 1 and providing the common mode component associated with the second common mode encoded high-speed clock frequency f 2 ;
amplifying the differential mode components associated with the first differential mode encoded high-speed clock frequency f 1 resulting in an amplified in-phase and out of phase component associated with the first differential mode encoded high-speed clock frequency f 1 ;
amplifying the common mode component associated with the second common mode encoded high-speed clock frequency f 2 ; and
selecting the differential amplifier or the common mode amplifier for performing the amplification operation.
23. The method of claim 22 , wherein the common mode component associated with the second common mode encoded high-speed clock frequency f 2 is converted to an amplified differential mode component.
24. The method of claim 22 provides either the amplified differential mode components associated with the first differential mode encoded high-speed clock frequency f 1 or the differential mode component associated with the second common mode encoded high-speed clock frequency f 2 to a plurality of transceivers.
25. A two wire-based method of clock amplification comprising:
receiving a first combined component from a first wire of a two wire-based conductor bus and receiving a second combined component from a second wire of the two wire-based conductor bus, wherein:
the first combined component contains an in-phase component associated with a first high-speed clock frequency f 1 encoded in a differential mode and a common mode component associated with a second high-speed clock frequency f 2 encoded in a common mode,
the second combined component contains an out of phase component associated with the first differential mode encoded high-speed clock frequency f 1 and the common mode component associated with the second common mode encoded high-speed clock frequency f 2 ,
suppressing the common mode components in the first and second combined component associated with the second common mode encoded high-speed clock frequency f 2 and providing the differential mode components associated with the first differential mode encoded high-speed clock frequency f 1 ;
suppressing the in-phase and out of phase components in the first and second combined component associated with the first differential mode encoded high-speed clock frequency f 1 and providing the common mode component associated with the second common mode encoded high-speed clock frequency f 2 ;
amplifying the differential mode component associated with the first differential mode encoded high-speed clock frequency f 1 resulting in an amplified in-phase and out of phase component associated with the first differential mode encoded high-speed clock frequency f 1 ;
amplifying the common mode component associated with the second common mode encoded high-speed clock frequency f 2 ;
combining the amplified in-phase component associated with the first differential mode encoded high-speed clock frequency f 1 with the amplified common mode component associated with the second common mode encoded high-speed clock frequency f 2 resulting in a first amplified combined component; and
combining the amplified out of phase component associated with the first differential mode encoded high-speed clock frequency f 1 with the amplified common mode component associated with the second common mode encoded high-speed clock frequency f 2 resulting in a second amplified combined component.
26. The method of claim 25 , wherein the first amplified combined component is transmitted on the first wire of the two wire-based conductor bus.
27. The method of claim 25 , wherein the second amplified combined component is transmitted on the second wire of the two wire-based conductor bus.