Enabling or disabling on-die error-correcting code for a memory built-in self-test
Implementations described herein relate to enabling or disabling on-die error-correcting code for a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, whether the memory built-in self-test is to be performed with on-die error-correcting code (ECC) disabled or with on-die ECC enabled. The memory device may perform the memory built-in self-test, and selectively test for one or more single-bit errors, based on identifying whether the memory built-in self-test is to be performed with the on-die ECC disabled or with the on-die ECC enabled.
1 . A memory device, comprising:
one or more components configured to:
read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device;
identify, based on the one or more bits, whether the memory built-in self-test is to be performed with on-die error-correcting code (ECC) disabled or with on-die ECC enabled; and
perform the memory built-in self-test, and selectively test for one or more single-bit errors, based on identifying whether the memory built-in self-test is to be performed with the on-die ECC disabled or with the on-die ECC enabled.
2 . The memory device of claim 1 , wherein a first state of the one or more bits indicates that the memory built-in self-test is to be performed with the on-die ECC disabled, and a second state of the one or more bits indicates that the memory built-in self-test is to be performed with the on-die ECC enabled.
3 . The memory device of claim 1 , wherein the one or more components, to perform the memory built-in self-test and selectively test for the one or more single-bit errors, are configured to perform the memory built-in self-test and test for the one or more single-bit errors based on identifying that the memory built-in self-test is to be performed with the on-die ECC disabled.
4 . The memory device of claim 1 , wherein the one or more components, to perform the memory built-in self-test and selectively test for the one or more single-bit errors, are configured to perform the memory built-in self-test without testing for the one or more single-bit errors based on identifying that the memory built-in self-test is to be performed with the on-die ECC enabled.
5 . The memory device of claim 1 , wherein a single-bit error indicates a change in a bit of the memory device from a first state to a second state, and a multiple-bit error indicates a change in multiple bits, of a set of bits of the memory device, from the first state to the second state.
6 . The memory device of claim 1 , wherein the one or more components are further configured to:
identify one or more single-bit errors or one or more multiple-bit errors based on performing the memory built-in self-test; and
initiate a repair procedure for repairing the one or more single-bit errors or the one or more multiple-bit errors.
7 . The memory device of claim 6 , wherein the one or more components, to initiate the repair procedure for repairing the one or more single-bit errors or the one or more multiple-bit errors, are configured to initiate the repair procedure based on a value of the one or more bits that are stored in the mode register of the memory device.
8 . The memory device of claim 1 , wherein the one or more components, to perform the memory built-in self-test, are configured to perform the memory built-in self-test, and selectively test for the one or more single-bit errors, for all memory sections of a plurality of memory sections associated with the memory device.
9 . The memory device of claim 1 , wherein the one or more components, to perform the memory built-in self-test, are configured to perform the memory built-in self-test, and selectively test for the one or more single-bit errors, for one or more memory sections, but fewer than all memory sections, of a plurality of memory sections associated with the memory device.
10 . The memory device of claim 9 , wherein the one or more components are further configured to read a bit that is stored in a section identifier mode register of the memory device,
wherein a first value of the bit indicates that a memory section, of the plurality of memory sections and corresponding to the bit, is to be tested, and
wherein a second value of the bit indicates that the memory section is not to be tested.
11 . A system, comprising:
a host device configured to:
obtain an indication of whether a memory built-in self-test for a memory device is to be performed with on-die error-correcting code (ECC) disabled or with on-die ECC enabled; and
transmit, to the memory device, a mode register write command to write one or more bits, that indicate whether the memory built-in self-test is to be performed with the on-die ECC disabled or with the on-die ECC enabled, to a mode register of the memory device; and
the memory device, wherein the memory device is configured to:
read the one or more bits from the mode register of the memory device; and
perform the memory built-in self-test, and selectively test for one or more single-bit errors, based on identifying whether the memory built-in self-test is to be performed with the on-die ECC disabled or with the on-die ECC enabled.
12 . The system of claim 11 , wherein the host device, to obtain the indication of whether the memory built-in self-test is to be performed with the on-die ECC disabled or with the on-die ECC enabled, is configured to obtain an indication that the on-die ECC is to be automatically disabled while the memory built-in self-test is being performed.
13 . The system of claim 12 , wherein the host device, to transmit the mode register write command, is configured to transmit a mode register write command to write one or more bits, to the mode register of the memory device, and each time that the memory built-in self-test is performed, indicate that the memory built-in self-test is to be performed with the on-die ECC disabled.
14 . The system of claim 11 , wherein the host device, to obtain the indication of whether the memory built-in self-test is to be performed with the on-die ECC disabled or with the on-die ECC enabled, is configured to obtain the indication based on a memory device type associated with the memory device or an amount of testing resources that are capable of being used by the memory device.
15 . The system of claim 11 , wherein the host device, to obtain the indication of whether the memory built-in self-test is to be performed with the on-die ECC disabled or with the on-die ECC enabled, is configured to obtain the indication based on whether the memory built-in self-test has previously been performed with the on-die ECC enabled.
16 . A memory device, comprising:
one or more components configured to:
read one or more bits, that are stored in a mode register of the memory device, that indicate whether a memory built-in self-test is to be performed with on-die error-correcting code (ECC) disabled or with the on-die ECC enabled;
identify whether the memory built-in self-test for the memory device is to be performed with the on-die ECC disabled or with the on-die ECC enabled based on reading the one or more bits; and
perform the memory built-in self-test for the memory device based on identifying whether the memory built-in self-test is to be performed with the on-die ECC disabled or with the on-die ECC enabled.
17 . The memory device of claim 16 , wherein:
the memory built-in self-test is configured to test for one or more single-bit errors when the memory built-in self-test is performed with the on-die ECC disabled; and
the memory built-in self-test is configured to test for one or more multiple-bit errors, and not to test for the one or more single-bit errors, when the memory built-in self-test is performed with the on-die ECC enabled.
18 . The memory device of claim 16 , wherein, to identify whether the memory built-in self-test is to be performed with the on-die ECC disabled or with the on-die ECC enabled, the one or more components are configured to:
identify that the memory built-in self-test is always to be performed with the on-die ECC disabled.
19 . The memory device of claim 16 , wherein, to perform the memory built-in self-test, the one or more components are configured to:
perform the memory built-in self-test and test for one or more single-bit errors based on the one or more bits indicating that the memory built-in self-test is to be performed with the on-die ECC disabled; or
perform the memory built-in self-test without testing for one or more single-bit errors based on the one or more bits indicating that the memory built-in self-test is to be performed with the on-die ECC enabled.
20 . The memory device of claim 17 , wherein a single-bit error indicates a change in a bit of the memory device from a first state to a second state, and a multiple-bit error indicates a change in multiple bits, of a set of bits of the memory device, from the first state to the second state.