Method of operating memory device, memory device using the same, and memory system including the device

1. A memory device comprising:

a control logic configured to control an overall operation of the memory device;

a data storing unit configured to receive write data and write the write data according to control of the control logic and to output read data obtained by reading the write data; and

a detector configured for repeating generation of a comparison result based on the read data and a current determination result based on the comparison result and a previous determination result N times and to generate a final determination result according to a result of the repeating,

where N is an integer of at least 2,

wherein the final determination result indicates whether an error has occurred and a type of the error.

2. The memory device of claim 1 , wherein the data storage unit comprises a memory cell array comprising a plurality of memory cells, wherein the comparison result is a result of comparing the write data with the read data, wherein the write data is data to be written to a memory cell corresponding to a first address among the plurality of memory cells, and wherein the read data is data read from the memory cell corresponding to the first address after the write data is written to the memory cell corresponding to the first address.

3. The memory device of claim 1 , further comprising:

an address buffer configured to receive address information from an external device outside the memory device and to transmit the address information to the data storing unit according to the control of the control logic;

a command buffer configured to receive a command from the external device outside the memory device and to transmit the command to the control logic; and a data input/output circuit configured to exchange the read data and the write data with the external device outside the memory device or the data storing unit according to the control of the control logic,

wherein the data storing unit comprises:

a memory cell array comprising a plurality of memory cells, a plurality of word lines, and a plurality of bit lines;

a row decoder and row driver block configured to select at least one of the word lines according to the address information;

a column decoder and column driver block configured to select at least one of the bit lines according to the address information; and

a write driver and sense amplifier block configured to write the write data to at least one memory cell selected according to the address information or to read the read data from the at least one memory cell.

4. The memory device of claim 1 , wherein the detector comprises:

a data storing circuit configured to store the write data and to output the write data and the read data;

a data comparing circuit configured to compare the write data with the read data to generate the comparison result; and

a defective type determination circuit configured to generate the current determination result based on the comparison result and the previous determination result and to store the current determination result as the previous determination result.

5. The memory device of claim 4 ,

wherein the data storing circuit comprises a first latch configured to store the write data;

the data comparing circuit comprises an exclusive OR (XOR) gate configured to compare the write data with the read data; and

the defective type determination circuit comprises a second latch configured to store the previous determination result, an AND gate configured to compare the previous determination result with the current determination result, and a counter configured to count a number of times of generation of the current determination result.

6. The memory device of claim 2 , wherein when the control logic receives a test mode register set (MRS) command, the first address is determined based on the address information received from an external device outside the memory device and the write data is data that a data input/output circuit of the memory device receives from the external device.

7. The memory device of claim 2 , wherein when the control logic receives a built in self test (BIST) command, the first address is determined according to BIST address information determined by the control logic and the write data is determined by the control logic.

8. The memory device of claim 1 , wherein the data storage unit comprises a memory cell array comprising a plurality of memory cells, wherein the comparison result is a result of comparing a first read data among the read data with a second read data among the read data, wherein the first read data is data read from memory cells corresponding to a first address among the plurality of memory cells, and wherein the second read data is data read from the memory cells corresponding to the first address after the first read data is read and the write data is written to the memory cell corresponding to the first address.

9. The memory device of claim 8 , wherein the detector comprises:

a data storing circuit configured to store the first read data and to output the first read data and the second read data;

a data comparing circuit configured to compare the first read data with the second read data and to generate the comparison result; and

a defective type determination circuit configured to generate the current determination result based on the comparison result and the previous determination result and to store the current determination result as the previous determination result.

10. A memory system comprising:

a memory device including a plurality of memory cells; and

a memory controller configured to transmit a command for controlling the memory device,

wherein the memory device comprises:

a control logic configured to control an overall operation of the memory device according to the command;

a data storing unit configured to receive write data and write the write data according to control of the control logic and to output read data obtained by reading the write data; and

a write error rate (WER) detector configured for repeating generation of a comparison result based on the read data and a current determination result based on the comparison result and a previous determination result N times and to generate a final determination result according to a result of the repeating, where N is an integer of at least 2.

11. A method of operating a memory device, the method comprising:

generating a current determination result based on a previous determination result and a comparison result generated based on read data read from a memory cell corresponding to a first address;

storing the current determination result as the previous determination result;

repeating the generating the current determination result and the storing the current determination result until the current determination result is generated N times,

where N is an integer of at least 1; and generating a final determination result according to a result of the repeating,

wherein the final determination result indicates whether the memory cell corresponding to the first address has an error and a type of the error.

12. The method of claim 11 , wherein the comparison result is a result of comparing write data to be written to the memory cell corresponding to the first address with the read data obtained by reading the write data from the memory cell corresponding to the first address.

13. The method of claim 12 , wherein the generating the current determination result comprises:

storing the write data in a detector that generates the current determination result; writing the write data to the memory cell corresponding to the first address; and

generating the comparison result based on the read data obtained by reading the write data from the memory cell corresponding to the first address and the write data stored in the detector.

14. The method of claim 13 , wherein the generating the current determination result further comprises receiving a mode register set (MRS) command, address information designating the first address, and the write data.

15. The method of claim 13 , further comprising receiving a built in self test (BIST) command and determining the first address and the write data.

16. The method of claim 11 , wherein the comparison result is a result of comparing first read data read from the memory cell corresponding to the first address and second read data read from the memory cell corresponding to the first address after the first read data is read.

17. The method of claim 16 , wherein the generating the current determination result comprises:

storing the first read data in a detector that generates the current determination result;

writing write data to the memory cell corresponding to the first address; and

generating the comparison result based on the second read data obtained by reading the write data from the memory cell corresponding to the first address and the first read data stored in the detector.

18. The method of claim 17 , wherein the generating the current determination result further comprises receiving a test mode register set (MRS) command, address information designating the first address, and the write data.

19. The method of claim 17 , further comprising receiving a built in self test (BIST) command and determining the first address and the write data.

20. The method of claim 11 , wherein N is determined based on a write error rate of a memory cell array.