Absorption enhancement structure to increase quantum efficiency of image sensor
Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a mask layer on a first side of a semiconductor substrate. The mask layer comprises a plurality of sidewalls defining a plurality of openings. A first etch process is performed on the semiconductor substrate to form a plurality of recesses within the semiconductor substrate. A second etch process is performed on the semiconductor substrate to expand the plurality of recesses and form a plurality of protrusions that comprise curved opposing sidewalls.
1 . A method for forming an integrated chip, comprising:
forming a photodetector in a semiconductor substrate; and
forming a plurality of column structures in a first side of the semiconductor substrate and over the photodetector, wherein forming the plurality of column structures includes performing a first removal process on the semiconductor substrate to form a plurality of first recessed surfaces in the semiconductor substrate and performing a second removal process on the semiconductor substrate to form a plurality of second recessed surfaces in the semiconductor substrate different from the first recessed surfaces.
2 . The method of claim 1 , wherein the plurality of first recessed surfaces are removed by the second removal process.
3 . The method of claim 1 , wherein the first recessed surfaces are flat, and wherein the second recessed surfaces are curved and define sidewalls of the column structures.
4 . The method of claim 1 , wherein the first removal process and the second removal process respectively include a dry etch, wherein the dry etch of the first removal process is different from the dry etch of the second removal process.
5 . The method of claim 4 , further comprising:
performing a reflectivity test on the plurality of column structures to measure a reflectivity of the plurality of column structures; and
performing a third removal process on the semiconductor substrate based at least in part on the measured reflectivity.
6 . The method of claim 1 , further comprising:
performing a third removal process on the plurality of column structures, wherein the second removal process forms lower sidewalls of the column structures and the third removal process forms upper sidewalls of the column structures, wherein the lower sidewalls are different from the upper sidewalls.
7 . The method of claim 1 , further comprising:
forming an interconnect structure on a second side of the semiconductor substrate, wherein the first side is opposite the second side, wherein the interconnect structure is formed before the plurality of column structures; and
forming an isolation structure in the semiconductor substrate and around the photodetector, wherein the isolation structure is formed after the plurality of column structures.
8 . The method of claim 1 , further comprising:
forming a first dielectric layer on the first side of the semiconductor substrate and lining the plurality of column structures; and
forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer comprises a plurality of protrusions spaced between adjacent column structures in the plurality of column structures, and wherein a top surface of the second dielectric layer is substantially flat.
9 . A method for forming an integrated chip, comprising:
forming a photodetector in a semiconductor substrate;
forming a plurality of protrusions along a first surface of the semiconductor substrate and over the photodetector, wherein forming the plurality of protrusions comprises:
performing a first removal process on the semiconductor substrate to form a plurality of recesses extending into the semiconductor substrate; and
performing a second removal process on the semiconductor substrate to expand the plurality of recesses and form the plurality of protrusions, wherein the plurality of protrusions respectively comprise curved opposing sidewalls.
10 . The method of claim 9 , wherein before the second removal process, sidewalls of the semiconductor substrate defining the plurality of recesses are straight.
11 . The method of claim 9 , further comprising:
performing a third removal process on the semiconductor substrate to further expand the plurality of recesses.
12 . The method of claim 11 , wherein the first removal process and the second removal process respectively comprise a dry etch, and wherein the third removal process comprises a wet etch.
13 . The method of claim 9 , further comprising:
forming a dielectric layer lining the plurality of protrusions, wherein a thickness of the dielectric layer is less than a height of the plurality of protrusions.
14 . The method of claim 9 , further comprising:
forming a dielectric structure over the semiconductor substrate and laterally surrounding each protrusion in the plurality of protrusions, wherein the dielectric structure comprises a plurality of curved lower surfaces arranged below a top of the plurality of protrusions.
15 . The method of claim 9 , wherein a width of a first protrusion of the plurality of protrusions increases at a first rate from a top surface of the first protrusion to a first point below the top surface of the first protrusion and increases at a second rate from the first point in a direction towards the photodetector, wherein the first rate is different from the second rate.
16 . The method of claim 15 , wherein a first distance between the top surface of the first protrusion and the first point is less than a second distance between the first point and a bottom of the first protrusion.
17 . A method for forming an integrated chip, comprising:
forming a photodetector in a semiconductor substrate;
forming a plurality of recesses into a first side of the semiconductor substrate, wherein forming the plurality of recesses comprises:
performing a first etch on the first side of the semiconductor substrate to form first openings in the semiconductor substrate and over the photodetector;
performing a second etch the semiconductor substrate to increase a depth of the first openings and define the plurality of recesses; and
wherein a first recess in the plurality of recesses is defined by an upper surface of the semiconductor substrate on the first side, wherein a slope of the upper surface of the semiconductor substrate defining the first recess continuously increases while moving from a first point aligned with a bottom of the first recess to a second point aligned with a top of the first recess.
18 . The method of claim 17 , wherein the second etch forms the upper surface of the semiconductor substrate.
19 . The method of claim 17 , wherein a first segment of the first recess is defined between the first point and the second point, wherein an angle defined between the first segment of the first recess and a horizontal line parallel to a bottom surface of the semiconductor substrate is within a range of about 30 to 120 degrees.
20 . The method of claim 17 , wherein the semiconductor substrate further comprises a lateral surface above the top of the first recess.
21 . The method of claim 17 , wherein a width of the first recess is greater than a depth of the first recess.