Operation stage of pipeline analog-to-digital converter and analog-to-digital converter thereof
An ADC receives a first input signal and a second input signal and outputs a digital signal. The first input signal is a common-mode voltage plus a voltage difference, and the second input signal is the common-mode voltage minus the voltage difference. The ADC includes a voltage conversion circuit and multiple comparators. The voltage conversion circuit generates an intermediate voltage according to the first input signal, the second input signal, and the common-mode voltage. The comparators compare the intermediate voltage with N times a reference voltage, where N is greater than or equal to negative one and less than or equal to one. The intermediate voltage is the common-mode voltage plus or minus M times the voltage difference, where M is two to the power of R, and R is a positive integer.
1 . An operation stage of a pipeline analog-to-digital converter (pipeline ADC), wherein the operation stage is configured to generate a first output signal and a second output signal according to a first input signal and a second input signal, the first input signal is a common-mode voltage plus a voltage difference, and the second input signal is the common-mode voltage minus the voltage difference, the operation stage comprising:
a voltage conversion circuit configured to generate an intermediate voltage according to the first input signal, the second input signal, and the common-mode voltage;
a plurality of comparators configured to compare the intermediate voltage with N times a first reference voltage to generate a digital signal, wherein N is greater than or equal to negative one and less than or equal to one;
a multiplexer coupled to the comparators and configured to generate a second reference voltage and a third reference voltage according to the digital signal; and
a multiplication circuit configured to generate the first output signal and the second output signal according to the first input signal, the second input signal, the second reference voltage, and the third reference voltage;
wherein the intermediate voltage is the common-mode voltage plus M times the voltage difference or the common-mode voltage minus M times the voltage difference, M is two to the power of R, and R is a positive integer.
2 . The operation stage of claim 1 , wherein the comparators compare the intermediate voltage with the first reference voltage and compare the intermediate voltage with a negative value of the first reference voltage.
3 . The operation stage of claim 2 , wherein M is equal to two, and the voltage conversion circuit comprises:
a capacitor having a first terminal and a second terminal;
a first switch having a third terminal and a fourth terminal, wherein the third terminal receives one of the first input signal and the second input signal, and the fourth terminal is coupled to the first terminal;
a second switch having a fifth terminal and a sixth terminal, wherein the fifth terminal is coupled to the first terminal, and the sixth terminal receives the common-mode voltage; and
a third switch having a seventh terminal and an eighth terminal, wherein the seventh terminal is coupled to the second terminal, and the eighth terminal receives another one of the first input signal and the second input signal.
4 . The operation stage of claim 3 , wherein when a clock is at a first level, the first switch is turned on, the second switch is turned off, and the third switch is turned on; when the clock is at a second level, the first switch is turned off, the second switch is turned on, and the third switch is turned off.
5 . The operation stage of claim 2 , wherein M is equal to two, and the voltage conversion circuit comprises:
a first capacitor having a first terminal and a second terminal;
a first switch having a third terminal and a fourth terminal, wherein the third terminal receives the first input signal, and the fourth terminal is coupled to the first terminal;
a second switch having a fifth terminal and a sixth terminal, wherein the fifth terminal is coupled to the first terminal, and the sixth terminal receives the common-mode voltage; and
a third switch having a seventh terminal and an eighth terminal, wherein the seventh terminal is coupled to the second terminal, and the eighth terminal receives the second input signal;
a second capacitor having a ninth terminal and a tenth terminal;
a fourth switch having an eleventh terminal and a twelfth terminal, wherein the eleventh terminal receives the second input signal, and the twelfth terminal is coupled to the ninth terminal;
a fifth switch having a thirteenth terminal and a fourteenth terminal, wherein the thirteenth terminal is coupled to the ninth terminal, and the fourteenth terminal receives the common-mode voltage; and
a sixth switch having a fifteenth terminal and a sixteenth terminal, wherein the fifteenth terminal is coupled to the second terminal, and the sixteenth terminal receives the first input signal.
6 . The operation stage of claim 5 , wherein when a clock is a first level, the first switch is turned on, the second switch is turned off, the third switch is turned on, the fourth switch is turned on, the fifth switch is turned off, and the sixth switch is turned on; when the clock is at a second level, the first switch is turned off, the second switch is turned on, the third switch is turned off, the fourth switch is turned off, the fifth switch is turned on, and the sixth switch is turned off.
7 . The operation stage of claim 2 , wherein M is equal to four, and the voltage conversion circuit comprises:
a first capacitor having a first terminal and a second terminal;
a second capacitor having a third terminal and a fourth terminal;
a first switch having a fifth terminal and a sixth terminal, wherein the fifth terminal receives a first signal, and the sixth terminal is coupled to the first terminal;
a second switch having a seventh terminal and an eighth terminal, wherein the seventh terminal is coupled to the first terminal, and the eighth terminal receives the common-mode voltage;
a third switch having a ninth terminal and a tenth terminal, wherein the ninth terminal is coupled to the second terminal, and the tenth terminal receives a second signal;
a fourth switch having an eleventh terminal and a twelfth terminal, wherein the eleventh terminal is coupled to the second terminal, and the twelfth terminal is coupled to the third terminal;
a fifth switch having a thirteenth terminal and a fourteenth terminal, wherein the thirteenth terminal is coupled to the third terminal, and the fourteenth terminal receives the first signal; and
a sixth switch having a fifteenth terminal and a sixteenth terminal, wherein the fifteenth terminal is coupled to the fourth terminal, and the sixteenth terminal receives the second signal;
wherein the first signal is one of the first input signal and the second input signal, and the second signal is another one of the first input signal and the second input signal.
8 . The operation stage of claim 7 , wherein when a clock is at a first level, the first switch is turned on, the second switch is turned off, the third switch is turned on, the fourth switch is turned off, the fifth switch is turned on, and the sixth switch is turned on; when the clock is at a second level, the first switch is turned off, the second switch is turned on, the third switch is turned off, the fourth switch is turned on, the fifth switch is turned off, and the sixth switch is turned off.
9 . An analog-to-digital converter (ADC), wherein the ADC is configured to receive a first input signal and a second input signal and output a digital signal, the first input signal is a common-mode voltage plus a voltage difference, and the second input signal is the common-mode voltage minus the voltage difference, the ADC comprising:
a voltage conversion circuit configured to generate an intermediate voltage according to the first input signal, the second input signal, and the common-mode voltage; and
a plurality of comparators configured to compare the intermediate voltage with N times a reference voltage, wherein N is greater than or equal to negative one and less than or equal to one;
wherein the intermediate voltage is the common-mode voltage plus M times the voltage difference or the common-mode voltage minus M times the voltage difference, M is two to the power of R, and R is a positive integer.
10 . The ADC of claim 9 , wherein the comparators compare the intermediate voltage with the reference voltage and compare the intermediate voltage with a negative value of the reference voltage.
11 . The ADC of claim 10 , wherein M is equal to two, and the voltage conversion circuit comprises:
a capacitor having a first terminal and a second terminal;
a first switch having a third terminal and a fourth terminal, wherein the third terminal receives one of the first input signal and the second input signal, and the fourth terminal is coupled to the first terminal;
a second switch having a fifth terminal and a sixth terminal, wherein the fifth terminal is coupled to the first terminal, and the sixth terminal receives the common-mode voltage; and
a third switch having a seventh terminal and an eighth terminal, wherein the seventh terminal is coupled to the second terminal, and the eighth terminal receives another one of the first input signal and the second input signal.
12 . The ADC of claim 11 , wherein when a clock is a first level, the first switch is turned on, the second switch is turned off, and the third switch is turned on; when the clock is at a second level, the first switch is turned off, the second switch is turned on, and the third switch is turned off.
13 . The ADC of claim 10 , wherein M is equal to two, and the voltage conversion circuit comprises:
a first capacitor having a first terminal and a second terminal;
a first switch having a third terminal and a fourth terminal, wherein the third terminal receives the first input signal, and the fourth terminal is coupled to the first terminal;
a second switch having a fifth terminal and a sixth terminal, wherein the fifth terminal is coupled to the first terminal, and the sixth terminal receives the common-mode voltage; and
a third switch having a seventh terminal and an eighth terminal, wherein the seventh terminal is coupled to the second terminal, and the eighth terminal receives the second input signal;
a second capacitor having a ninth terminal and a tenth terminal;
a fourth switch having an eleventh terminal and a twelfth terminal, wherein the eleventh terminal receives the second input signal, and the twelfth terminal is coupled to the ninth terminal;
a fifth switch having a thirteenth terminal and a fourteenth terminal, wherein the thirteenth terminal is coupled to the ninth terminal, and the fourteenth terminal receives the common-mode voltage; and
a sixth switch having a fifteenth terminal and a sixteenth terminal, wherein the fifteenth terminal is coupled to the second terminal, and the sixteenth terminal receives the first input signal.
14 . The ADC of claim 13 , wherein when a clock is a first level, the first switch is turned on, the second switch is turned off, the third switch is turned on, the fourth switch is turned on, the fifth switch is turned off, and the sixth switch is turned on; when the clock is at a second level, the first switch is turned off, the second switch is turned on, the third switch is turned off, the fourth switch is turned off, the fifth switch is turned on, and the sixth switch is turned off.
15 . The ADC of claim 10 , wherein M is equal to four, and the voltage conversion circuit comprises:
a first capacitor having a first terminal and a second terminal;
a second capacitor having a third terminal and a fourth terminal;
a first switch having a fifth terminal and a sixth terminal, wherein the fifth terminal receives a first signal, and the sixth terminal is coupled to the first terminal;
a second switch having a seventh terminal and an eighth terminal, wherein the seventh terminal is coupled to the first terminal, and the eighth terminal receives the common-mode voltage;
a third switch having a ninth terminal and a tenth terminal, wherein the ninth terminal is coupled to the second terminal, and the tenth terminal receives a second signal;
a fourth switch having an eleventh terminal and a twelfth terminal, wherein the eleventh terminal is coupled to the second terminal, and the twelfth terminal is coupled to the third terminal;
a fifth switch having a thirteenth terminal and a fourteenth terminal, wherein the thirteenth terminal is coupled to the third terminal, and the fourteenth terminal receives the first signal; and
a sixth switch having a fifteenth terminal and a sixteenth terminal, wherein the fifteenth terminal is coupled to the fourth terminal, and the sixteenth terminal receives the second signal;
wherein the first signal is one of the first input signal and the second input signal, and the second signal is another one of the first input signal and the second input signal.
16 . The ADC of claim 15 , wherein when a clock is at a first level, the first switch is turned on, the second switch is turned off, the third switch is turned on, the fourth switch is turned off, the fifth switch is turned on, and the sixth switch is turned on; when the clock is at a second level, the first switch is turned off, the second switch is turned on, the third switch is turned off, the fourth switch is turned on, the fifth switch is turned off, and the sixth switch is turned off.