Successive approximation register analog-digital converter and method for operating the same

1. A successive approximation register analog digital converter (SAR ADC), comprising:

a first conversion unit including a correction capacitor array and a bit capacitor array 2 N-1 less than the number of bits;

a second conversion unit configured to differentially operate with the first conversion unit;

a comparator configured to output a voltage of a high level or a low level of each capacitor according to output voltages of the first and second conversion units;

a successive approximation register (SAR) logic unit configured to receive an output voltage of the comparator to convert the received output voltage into a digital signal; and

a correction logic unit configured to receive the digital signal converted by the SAR logic unit and to correct a digital signal of the bit capacitor array using a correction digital signal of the correction capacitor array of the received digital signal,

wherein after an input analog signal is sampled, outputs of the first and second conversion units are connected to input terminals of the comparator to determine a digital value corresponding to the most significant bit (MSB) according to the output voltage of the comparator.

2. The SAR ADC of claim 1 , wherein the correction capacitor array is formed between any one of a common mode voltage, a first reference voltage and a second reference voltage and the input terminal of the comparator, and includes a first correction capacitor and a second correction capacitor.

3. The SAR ADC of claim 2 , wherein the common mode voltage has an intermediate value of the first and second reference voltages.

4. The SAR ADC of claim 2 , wherein the first correction capacitor calculates a value equal to a value of a capacitor corresponding to the LSB of the bit capacitor array.

5. The SAR ADC of claim 4 , wherein the correction logic unit determines that no error has occurred when a digital value of the first correction capacitor is equal to the digital value corresponding to the LSB and a digital value of the second correction capacitor is equal to an inverted value of the digital value corresponding to the LSB.

6. The SAR ADC of claim 5 , wherein the correction logic unit determines that an error has occurred in the digital value of the first correction capacitor and uses the digital value corresponding to the LSB as it is, when the digital values of the first and second correction capacitors are equal to the inverted value of the digital value corresponding to the LSB.

7. The SAR ADC of claim 6 , wherein the correction logic unit adds “1” to a total code value when the digital value corresponding to the LSB and the digital values of the first and second correction capacitors are “1,1,1” or “0,1,0,” respectively, and the logic correction unit subtracts “1” from the total code value, when the digital value corresponding to the LSB and the digital values of the first and second correction capacitors are “1,0,1” or “0,0,0,” respectively.

8. A method of driving a successive approximation register analog digital converter (SAR ADC) including a bit capacitor array and first and second correction capacitors, comprising:

sampling an input analog voltage of the bit capacitor array;

determining a digital value of “0” or “1” of a bit corresponding to the most significant bit (MSB);

determining digital values of “1” or “0” from a bit capacitor corresponding to a bit next to the MSB to the bit capacitor corresponding to the LSB by carrying out a successive approximation operation;

determining digital values of “1” or “0” of the first and second correction capacitors according to the digital value corresponding to the LSB by the successive approximation operation without driving the bit capacitor corresponding to the LSB; and

correcting the digital values of the bit capacitors according to the digital values of the first and second correction capacitors.

9. The method of claim 8 , wherein in the sampling, a bottom plate of the first correction capacitor is connected to the input analog voltage and a bottom plate of the second capacitor is connected to a common mode voltage.

10. The method of claim 9 , wherein the common mode voltage has an intermediate value of first and second reference voltages.

11. The method of claim 10 , wherein correcting the digital value of the bit capacitor includes determining that no error has occurred when the digital value of the first correction capacitor is equal to the digital value corresponding to the LSB and the digital value of the second correction capacitor is equal to an inverted value of the digital value corresponding to the LSB.

12. The method of claim 11 , wherein correcting the digital value of the bit capacitor includes determining that an error is in the first correction capacitor and using the digital value corresponding to the LSB as it is when the digital values of the first and second correction capacitors are equal to the inverted value of the digital value corresponding to the LSB.

13. The method of claim 12 , wherein correcting the digital value of the bit capacitor includes adding “1” to a total code value when the digital value corresponding to the LSB and the digital values of the first and second correction capacitors are “1,1,1” or “0,1,0,” respectively and subtracting “1” from the total code value when the digital value corresponding to the LSB and the digital values of the first and second correction capacitors are “1,0,1” or “0,0,0,” respectively.

14. The method of claim 8 , wherein the SAR ADC further includes another bit capacitor array configured to reversely connect a power source as compared with the bit capacitor array and,

determining the digital value of “1” or “0” of the bit corresponding to the MSB includes determining an output of a comparator by connecting an output of the other bit capacitor array to which the power source is reversely connected as compared with the bit capacitor array to input terminals of the comparator.