Non-volatile static random access memory (NVSRAM) with multiple magnetic tunnel junction cells
Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.
1. An integrated circuit, comprising:
a plurality of first memory cells including a first reference memory cell, wherein the first reference memory cell stores a first bit;
a plurality of second memory cells including a second reference memory cell, wherein the second reference memory cell stores a second bit; and
a third memory cell disposed between the plurality of first memory cells and plurality of second memory cells, wherein the third memory cell has a first port and a second port coupled to the first reference memory cell and the second reference memory cell, respectively;
wherein the first bit is independent of the second bit,
wherein the first reference cell presents an average resistance of a first resistance and a second resistance provided to the second port, and the second reference cell present the average resistance provided to the first port.
2. The integrated circuit of claim 1 , wherein the first and second memory cells are each a magnetic tunnel junction (MTJ) cell, and the third memory cell is a static random access memory (SRAM) cell.
3. The integrated circuit of claim 1 , wherein a pinned layer of the first reference cell is connected to a first reference line, and a pinned layer of the second reference cell is connected to a second reference line.
4. The integrated circuit of claim 1 , wherein the first and second memory cells are each a magnetic tunnel junction (MTJ) cell.
5. The integrated circuit of claim 4 , wherein a programmed resistance state of a selected one of the second memory cells, other than the second reference cell, is configured to be provided to the first port, and a programmed resistance state of a selected one of the first memory cells, other than the first reference cell, is configured to be provided to the second port.
6. The integrated circuit of claim 5 , wherein the programmed resistance state is equal to either the first resistance or the second resistance.
7. The integrated circuit of claim 1 , further comprising:
a plurality of fourth memory cells including a fourth reference memory cell, wherein the fourth reference memory cell stores a third bit;
a plurality of fifth memory cells including a fifth reference memory cell, wherein the fifth reference memory cell stores a fourth bit; and
a sixth memory cell disposed between the plurality of fourth memory cells and plurality of fifth memory cells, wherein the sixth memory cell has a third port and a fourth port coupled to the fourth reference memory cell and the fifth reference memory cell, respectively;
wherein the third bit is independent of the fourth bit.
8. The integrated circuit of claim 7 , wherein a pinned layer of each of the first and fourth reference cells is connected to a first reference line, and a pinned layer of each of the second and fifth reference cells is connected to a second reference line.
9. The integrated circuit of claim 1 , wherein the third memory cell is configured to amplify a voltage difference between the first port and the second port.
10. The integrated circuit of claim 9 , wherein the first reference cell presents an average resistance of a first resistance and a second resistance while one of the plurality of second memory cells, other than the second reference cell, is selected to be read, and the second reference cell presents the average resistance while one of the plurality of first memory cells, other than the first reference cell, is selected to be read.
11. The integrated circuit of claim 10 , wherein a bit stored by the selected first or second memory cell is configured to be determined based on the amplified voltage difference.
12. An integrated circuit, comprising:
a plurality of first magnetic tunnel junction (MTJ) cells including a first reference MTJ cell, wherein the first reference MTJ cell stores a first bit;
a plurality of second MTJ cells including a second reference MTJ cell, wherein the second reference MTJ cell stores a second bit; and
a static random access memory (SRAM) cell disposed between the plurality of first MTJ cells and plurality of second MTJ cells, wherein the SRAM cell has a first port and a second port coupled to the first reference MTJ cell and the second reference MTJ cell, respectively;
wherein the first bit is independent of the second bit.
13. The integrated circuit of claim 12 , wherein the first reference MTJ cell presents an average resistance of a first resistance and a second resistance while one of the plurality of second MTJ cells, other than the second reference MTJ cell, is selected to be read, and the second reference MTJ cell presents the average resistance while one of the plurality of first MTJ cells, other than the first reference MTJ cell, is selected to be read.
14. The integrated circuit of claim 13 , wherein a pinned layer of the first reference MTJ cell is connected to a first reference line, and a pinned layer of the second reference MTJ cell is connected to a second reference line.
15. The integrated circuit of claim 13 , wherein the average resistance of the first reference MTJ cell is provided to the second port, and the average resistance of the second reference MTJ cell is provided to the first port.
16. The integrated circuit of claim 15 , wherein a programmed resistance state of the selected second MTJ cell is configured to be provided to the first port, and a programmed resistance state of the selected first MTJ cell is configured to be provided to the second port.
17. The integrated circuit of claim 16 , wherein the programmed resistance state is equal to either the first resistance or the second resistance.
18. The integrated circuit of claim 12 , wherein the SRAM cell is configured to amplify a voltage difference between the first port and the second port.
19. An integrated circuit comprising:
plurality of first magnetic tunnel junction (MTJ) cells including a first reference MTJ cell, wherein the first reference MTJ cell stores a first bit;
a plurality of second MTJ cells including a second reference MTJ cell, wherein the second reference MTJ cell stores a second bit; and
a static random access memory (SRAM) cell disposed between the plurality of first MTJ cells and plurality of second MTJ cells, wherein the SRAM cell has a first port and a second port coupled to the first reference MTJ cell and the second reference MTJ cell, respectively;
wherein the first bit is independent of the second bit;
wherein the first reference MTJ cell presents an average resistance of a first resistance and a second resistance while one of the plurality of second MTJ cells, other than the second reference MTJ cell, is selected to be read, and the second reference MTJ cell presents the average resistance while one of the plurality of first MTJ cells, other than the first reference MTJ cell, is selected to be read.
20. The integrated circuit of claim 19 , wherein the average resistance of the first reference MTJ cell is provided to the second port, and the average resistance of the second reference MTJ cell is provided to the first port, and wherein a programmed resistance state of the selected second MTJ cell is configured to be provided to the first port, and a programmed resistance state of the selected first MTJ cell is configured to be provided to the second port.