Backup and/or restore of a memory circuit
Briefly, embodiments of claimed subject matter relate to backup of parameters, such as binary logic values, stored in nonvolatile memory, such as one or more SRAM cells. Binary logic values from a SRAM cell, for example, may be stored utilizing resistance states of a magnetic random-access memory (MRAM) element. Parameters stored in one or more MRAM elements may be restored to SRAM memory cells following a backup.
1. A method of performing a backup of a static random-access memory (SRAM) cell, comprising:
applying a SRAM cell supply voltage to the SRAM cell;
applying a word-line voltage to first and second access transistors to enable conduction of an electrical current through the first and second access transistors, wherein the first access transistor is configured to electrically couple a first bit-line to a first non-volatile memory element, and wherein the second access transistor is configured to electrically couple a second bit-line to a second non-volatile memory element;
applying, to the first bit-line coupled to a first input node of the SRAM cell and to a second bit-line coupled to the second input node of the SRAM cell, a voltage equal to a fraction of the SRAM cell supply voltage;
responsive to applying the fraction of the SRAM cell supply voltage, storing, in the first nonvolatile memory element coupled between the first access transistor and the first input node of the SRAM cell, a first binary logic value from the SRAM cell; and
responsive to applying the fraction of the SRAM cell supply voltage, storing, in the second nonvolatile memory element coupled between the second access transistor and the second input node of the SRAM cell, a second binary logic value from the SRAM cell; and
boosting the SRAM cell supply voltage by an amount approximately equal to about 20.0% to about 50.0% of a normal operating value of the SRAM cell supply voltage.
2. The method of claim 1 , wherein the first and second nonvolatile memory elements comprise magnetic random-access memory (MRAM).
3. The method of claim 1 , wherein the SRAM cell comprises six transistors.
4. The method of claim 1 , wherein the fraction of the SRAM cell supply voltage comprises a value of between 25.0% and 75.0% of the value of the SRAM cell supply voltage.
5. The method of claim 1 , further comprising restoring the first binary logic value from the first nonvolatile memory element to the SRAM cell, wherein the restoring comprises applying a word-line voltage substantially equal to a SRAM cell supply voltage while applying a reference voltage to the first bit-line and applying the reference voltage to the second bit-line.
6. The method of claim 1 , wherein the storing in the first nonvolatile memory element and the storing in the second nonvolatile memory element occur simultaneously.