DECISION FEEDBACK EQUALIZER SENSE AMPLIFIER CIRCUITS AND METHODS FOR DOUBLE DATA RATE NONVOLATILE MEMORY DEVICES

1 . An apparatus comprising:

a first circuit stage comprising a current amplifier circuit configured to receive a data input signal and a feedback signal; and

a second circuit stage comprising a voltage circuit coupled to the first circuit stage,

wherein:

the first circuit stage is configured to integrate a current based on the data input signal and the feedback signal;

the second circuit stage is configured to provide an output signal corresponding to a decision of a value of the data input signal; and

the apparatus is configured to operate with a double data rate clocking scheme.

2 . The apparatus of claim 1 , wherein:

the first circuit stage comprises a first input node and a second input node; and

the first circuit stage is further configured to integrate a first current and a second current based on a voltage difference between the first input node and the second input node.

3 . The apparatus of claim 1 , wherein the first circuit stage is further configured to:

receive a reference signal; and

integrate a first current and a second current based on a difference between the data input signal and the reference signal.

4 . The apparatus of claim 1 , wherein:

the first circuit stage comprises a first input node and a second input node; and

the first circuit stage is further configured to integrate a first current on a first parasitic capacitor based on a voltage at the first input node and integrate a second current on a second parasitic capacitor based on a voltage at the second input node.

5 . The apparatus of claim 1 , wherein:

the first circuit stage comprises a first input node, a second input node, a third input node and a fourth input node; and

the first circuit stage is further configured to integrate a first current on a first parasitic capacitor based on a voltage at the first input node, integrate a second current on a second parasitic capacitor based on a voltage at the second input node, integrate a third current on the first parasitic capacitor based on a voltage at the third input node, and integrate a fourth current on the second parasitic capacitor based on a voltage at the fourth input node.

6 . The apparatus of claim 1 , wherein:

the first circuit stage is further configured to generate a first intermediate output signal and a second intermediate output signal; and

the second circuit stage is further configured to provide the output signal based on a difference between the first intermediate output signal and the second intermediate output signal.

7 . The apparatus of claim 1 , wherein:

the first circuit stage is further configured to generate a first intermediate output signal and a second intermediate output signal; and

the second circuit stage is further configured to provide a first output signal and a second output signal based on the first intermediate output signal and the second intermediate output signal.

8 . The apparatus of claim 1 , wherein:

the first circuit stage is further configured to sample the data input signal based on an edge of a first clock signal; and

the second circuit stage is further configured to provided the output signal corresponding to a decision of a value of the sampled data input signal.

9 . The apparatus of claim 8 , wherein the first circuit stage and the second circuit stage are configured to reset based on an edge of a second clock signal.

10 . The apparatus of claim 9 , wherein the second clock signal is an inverted version of the first clock signal.

11 . The apparatus of claim 1 , comprising a decision feedback equalizer sense amplifier circuit.

12 . The apparatus of claim 1 , further comprising:

a non-volatile memory array coupled to the first circuit stage,

wherein data read from the non-volatile memory array comprises the data input signal.

13 . The apparatus of claim 1 , wherein the feedback signal corresponds to a decision of a value of previous data input signal.

14 . A system comprising:

a first decision feedback equalizer sense amplifier circuit comprising a first input node coupled to a data input signal, a second input node coupled to a reference signal, a third input node, a fourth input node, a first output node and a second output node; and

a second decision feedback equalizer sense amplifier circuit comprising a first input node coupled to the data input signal, a second input node coupled to the reference signal, a third input node coupled to the first output node of the first decision feedback equalizer sense amplifier circuit, a fourth input node coupled to the second output node of the first decision feedback equalizer sense amplifier circuit, a first output node coupled to the third input node of the first decision feedback equalizer sense amplifier circuit and a second output node coupled to the fourth input node of the first decision feedback equalizer sense amplifier circuit,

wherein the first decision feedback equalizer sense amplifier circuit and the second decision feedback equalizer sense amplifier circuit are configured to operate with a double data rate clocking scheme.

15 . The system of claim 14 , wherein the first decision feedback equalizer sense amplifier circuit and the second decision feedback equalizer sense amplifier circuit each include a current amplifier circuit and a voltage circuit coupled to the current amplifier circuit.

16 . The system of claim 14 , wherein the first decision feedback equalizer sense amplifier circuit comprises a first circuit stage configured to integrate a current based on the data input signal, a signal at the first output node of the second decision feedback equalizer sense amplifier circuit, and a signal at the second output node of the second decision feedback equalizer sense amplifier circuit.

17 . The system of claim 14 , wherein the second decision feedback equalizer sense amplifier circuit comprises a first circuit stage configured to integrate a current based on the data input signal, a signal at the first output node of the first decision feedback equalizer sense amplifier circuit, and a signal at the second output node of the first decision feedback equalizer sense amplifier circuit.

18 . The system of claim 14 , further comprising:

a first clock signal coupled to the first decision feedback equalizer sense amplifier circuit; and

a second clock signal coupled to the first decision feedback equalizer sense amplifier circuit,

wherein the second clock signal is an inverted version of the first clock signal.

19 . The system of claim 14 , further comprising:

a non-volatile memory array coupled to the first decision feedback equalizer sense amplifier circuit and the second decision feedback equalizer sense amplifier circuit,

wherein data read from the non-volatile memory array comprises the data input signal.

20 . A method comprising:

determining a distortion characteristic of a communication channel disposed between a non-volatile memory array and a memory controller interface that comprises a first decision feedback equalizer sense amplifier circuit; and

selectively activating a feedback circuit in the first decision feedback equalizer sense amplifier circuit based on the determined distortion characteristic,

wherein:

the feedback circuit in the first decision feedback equalizer sense amplifier circuit is configured to integrate a current based on a feedback signal from a second decision feedback equalizer sense amplifier circuit;

the first decision feedback equalizer sense amplifier circuit and the second decision feedback equalizer sense amplifier circuit are configured to operate with a double data rate clocking scheme.