IP Library › Granted Patent US 12,633,737
Granted Patent B2
US 12,633,737 · App. 18/670,477 · Granted May 19, 2026

Abnormality detection apparatus

Inventor: Kunihiko Matsuda (Kariya-city, JP)
Assignee: DENSO CORPORATION
H02H7/1227H02M1/32H02M7/48H02M7/5387H02M7/53873H02P27/06
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Quick Facts
Patent No.
US 12,633,737
App. No.
18/670,477
Granted
May 19, 2026
Kind
B2
Abstract

A monitoring voltage output unit outputs a monitoring voltage that has a positive correlation with the current flowing through a shunt resistor connected in series with an upper arm element and a lower arm element of each phase. A monitoring circuit monitors an inverter overcurrent abnormality due to an upper arm element or a lower arm element of one or more phases being stuck in an ON state based on the monitoring voltage. A comparator of the monitoring circuit outputs an overcurrent flag of a pulse signal when the monitoring voltage is larger than a reference value. A determination unit determines that an inverter overcurrent is abnormal and stop energization of an inverter, when a cumulative output time of the overcurrent flag of at least one phase reaches a time threshold or when number of outputs of the overcurrent flag reaches a number threshold.

Claims (29)

1 . An abnormality detection apparatus, comprising:

a control unit configured to cause an upper arm element and a lower arm element to perform complementary switching operations in an inverter in which the upper arm element and the lower arm element of multiple phases are bridge-connected;

a monitoring voltage output unit configured to output a monitoring voltage that has a positive correlation with current flowing through a shunt resistor connected in series with the upper arm element and the lower arm element of each phase; and

a monitoring circuit configured to monitor an inverter overcurrent abnormality due to an upper arm element or a lower arm element of one or more phases being stuck in an ON state based on the monitoring voltage during operation of the inverter,

wherein

the monitoring voltage output unit holds an output state of the monitoring voltage for a predetermined hold time from input of a trigger signal,

the monitoring circuit includes

a comparator configured to output an overcurrent flag of a pulse signal when the monitoring voltage is larger than a reference value, and

a determination unit configured to determine that an inverter overcurrent is abnormal and stop energization of the inverter, when a cumulative output time of the overcurrent flag of at least one phase reaches a time threshold.

2 . An abnormality detection apparatus, comprising:

a control unit configured to cause an upper arm element and a lower arm element to perform complementary switching operations in an inverter in which the upper arm element and the lower arm element of multiple phases are bridge-connected;

a monitoring voltage output unit configured to output a monitoring voltage that has a positive correlation with current flowing through a shunt resistor connected in series with the upper arm element and the lower arm element of each phase; and

a monitoring circuit configured to monitor an inverter overcurrent abnormality due to an upper arm element or a lower arm element of one or more phases being stuck in an ON state based on the monitoring voltage during operation of the inverter,

wherein

the monitoring voltage output unit holds an output state of the monitoring voltage for a predetermined hold time from input of a trigger signal,

the monitoring circuit includes

a comparator configured to output an overcurrent flag of a pulse signal when the monitoring voltage is larger than a reference value, and

a determination unit configured to determine that an inverter overcurrent is abnormal and stop energization of the inverter, when a cumulative output time of the overcurrent flag of at least one phase reaches a time threshold, and

the determination unit determines that there is the inverter overcurrent abnormality at the earliest timing of when a cumulative output time of the overcurrent flag reaches the time threshold for at least one phase, or when number of outputs of the overcurrent flag reaches a number threshold.

3 . The abnormality detection apparatus according to claim 1 , wherein

in an initial check of the monitoring circuit,

when the monitoring voltage output unit outputs a voltage larger than the reference value to the comparator as the monitoring voltage for diagnosis, the comparator outputs the overcurrent flag, and the determination unit determines that the inverter overcurrent abnormality occurs when the cumulative output time or number of outputs of the monitoring voltage for diagnosis satisfies an abnormality determination condition.

4 . The abnormality detection apparatus according to claim 1 , wherein

the control unit or the monitoring circuit identifies a phase in which the upper arm element or the lower arm element is stuck in the ON state based on an output of the comparator for each phase.

5 . The abnormality detection apparatus according to claim 2 , wherein

in an initial check of the monitoring circuit,

when the monitoring voltage output unit outputs a voltage larger than the reference value to the comparator as the monitoring voltage for diagnosis, the comparator outputs the overcurrent flag, and the determination unit determines that the inverter overcurrent abnormality occurs when the cumulative output time or number of outputs of the monitoring voltage for diagnosis satisfies an abnormality determination condition.

6 . The abnormality detection apparatus according to claim 2 , wherein

the control unit or the monitoring circuit identifies a phase in which the upper arm element or the lower arm element is stuck in the ON state based on an output of the comparator for each phase.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2024
From: MATSUDA, KUNIHIKO
To: DENSO CORPORATION
Reel/Frame 067493/0342 →
Priority Claims (1)
JP 2021-190218 · Nov 24, 2021 · national
Continuity (2)
Continuation PCTJP2022042558 · Nov 16, 2022
Related Publication 20240313523A1 · Sep 19, 2024
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