Clock generation for multi-phase converters
A multiphase switching voltage regulator is disclosed. The regulator includes a first clock generator circuit configured to receive a reference clock, and to generate M first clocks, where the M first clocks are phase separated by 360°/M, a plurality of phase extrapolator circuits, where the plurality of phase extrapolator circuits includes N phase extrapolator circuits, and a phase selector multiplexer configured to provide one of the M first clocks to each of the phase extrapolator circuits, where the N phase extrapolator circuits are configured to generate N output clocks, where the N output clocks are phase separated by 360°/N.
1. A voltage regulator, comprising:
a first clock generator circuit arranged to receive a reference clock signal, and to generate M first clock signals, wherein each of the M first clock signals are phase separated by 360°/M;
N phase extrapolator circuits, wherein N is not equal to M;
a phase selector multiplexer arranged to provide one of the M first clock signals to each of the N phase extrapolator circuits;
wherein the N phase extrapolator circuits are arranged to generate N output clock signals based in part on the M first clock signals received from the phase selector multiplexer,
wherein each of the N output clock signals are phase separated by 360°/N; and
wherein each of the N phase extrapolator circuits comprises:
a ramp generator circuit arranged to receive one of the M first clock signals and to generate a ramp signal in response to the received first clock signal.
2. The voltage regulator of claim 1 , wherein each of the N phase extrapolator circuits further comprises a comparator circuit arranged to compare the ramp signal to a programmable reference and to generate one of the N output clock signals based on the comparison, wherein the generated one output clock signal has a phase difference with respect to a phase of the received first clock signal which is dependent on a value of the programmable reference.
3. The voltage regulator of claim 2 , wherein each phase extrapolator circuit of the N phase extrapolator circuits is arranged to receive a particular one of the M first clock signals, and to generate a corresponding one of the N output clock signals, wherein the particular one of the N output clock signals has a phase difference relative to the received particular one first clock signal, and wherein the phase differences of the N output clock signals are controlled so that the N output clock signals are phase separated by 360°/N.
4. The voltage regulator of claim 2 , wherein the ramp signal changes monotonically, wherein the programmable reference has a minimum value and has a maximum value, and wherein a time difference between the ramp signal having a value corresponding with the programmable reference having a minimum value and the ramp signal having a value corresponding with the programmable reference having a maximum value is calibrated.
5. The voltage regulator of claim 4 , wherein the reference clock signal has a period, and wherein the time difference is about equal to about ¼ of the period of the reference clock signal.
6. The voltage regulator of claim 1 , further comprising a phase extrapolator controller arranged to change N output clock signals.
7. The voltage regulator of claim 1 , wherein the ramp signal changes monotonically with a rate of change determined by a calibration signal.
8. The voltage regulator of claim 7 , wherein the calibration signal is determined by a calibration controller, and wherein the voltage regulator is physically disconnectable from the calibration controller.
9. A method of operating a circuit, the method comprising:
receiving, by a first clock generator circuit, a reference clock signal;
generating M first clock signals, by the first clock generator circuit, wherein each of the M first clock signals are phase separated by 360°/M;
providing N phase extrapolator circuits, wherein N is not equal to M;
providing to one of the M first clock signals, by a phase selector multiplexer, to each of the N phase extrapolator circuits;
generate N output clock signals, by the N phase extrapolator circuits, based in part on the M first clock signals received from the phase selector multiplexer,
wherein each of the N output clock signals are phase separated by 360°/N; and
wherein each of the N phase extrapolator circuits comprises:
a ramp generator circuit arranged to receive one of the M first clock signals and to generate a ramp signal in response to the received first clock signal.
10. The method of claim 9 , wherein each of the N phase extrapolator circuits further comprises a comparator circuit arranged to compare the ramp signal to a programmable reference and to generate one of the N output clock signals based on the comparison, wherein the generated one output clock signal has a phase difference with respect to a phase of the received first clock signal which is dependent on a value of the programmable reference.
11. The method of claim 10 , wherein each phase extrapolator circuit of the N phase extrapolator circuits is arranged to receive a particular one of the M first clock signals, and to generate a corresponding one of the N output clock signals, wherein the particular one of the N output clock signals has a phase difference relative to the received particular one first clock signal, and wherein the phase differences of the N output clock signals are controlled so that the N output clock signals are phase separated by 360°/N.
12. The method of claim 10 , wherein the ramp signal changes monotonically, wherein the programmable reference has a minimum value and has a maximum value, and wherein a time difference between the ramp signal having a value corresponding with the programmable reference having a minimum value and the ramp signal having a value corresponding with the programmable reference having a maximum value is calibrated.
13. The method of claim 12 , wherein the reference clock signal has a period, and wherein the time difference is about equal to about ¼ of the period of the reference clock signal.
14. The method of claim 9 , further comprising changing N output clock signals by a phase extrapolator controller.
15. The method of claim 9 , wherein the ramp signal changes monotonically with a rate of change determined by a calibration signal.
16. The method of claim 15 , wherein the calibration signal is determined by a calibration controller.
17. A circuit comprising:
a first clock generator circuit arranged to receive a reference clock signal, and to generate M first clock signals, wherein each of the M first clock signals are phase separated by 360°/M;
N phase extrapolator circuits, wherein N is not equal to M;
a phase selector multiplexer arranged to provide one of the M first clock signals to each of the N phase extrapolator circuits;
wherein the N phase extrapolator circuits are arranged to generate N output clock signals based in part on the M first clock signals received from the phase selector multiplexer,
wherein each of the N output clock signals are phase separated by 360°/N; and
wherein each of the N phase extrapolator circuits comprises:
a ramp generator circuit arranged to receive one of the M first clock signals and to generate a ramp signal in response to the received first clock signal, and a comparator circuit arranged to compare the ramp signal to a programmable reference and to generate one of the N output clock signals based on the comparison.
18. The circuit of claim 17 , wherein the generated one output clock signal has a phase difference with respect to a phase of the received first clock signal which is dependent on a value of the programmable reference.
19. The circuit of claim 18 , wherein each phase extrapolator circuit of the N phase extrapolator circuits is arranged to receive a particular one of the M first clock signals, and to generate a corresponding one of the N output clock signals.
20. The circuit of claim 19 , wherein the particular one of the N output clock signals has a phase difference relative to the received particular one first clock signal, and wherein the phase differences of the N output clock signals are controlled so that the N output clock signals are phase separated by 360°/N.