Current balance circuit and multiphase DC-DC converter and current balance method thereof
The present invention discloses a current balance circuit for a multiphase DC-DC converter. The current balance circuit comprises a current error calculation circuit, for generating a plurality of current balance signals indicating imbalance levels of a plurality of inductor currents of a plurality of channels of the multiphase DC-DC converter according to a plurality of current sensing signals of the plurality of channels, a time shift circuit, for adjusting pulse widths of a plurality of clock signals according to the plurality of current balance signals, and a ramp generator, for deciding shift levels of a plurality of ramp signals according to the plurality of clock signals.
1. A current balance circuit for a multiphase DC-DC converter, comprising:
a current error calculation circuit, for generating a plurality of current balance signals indicating imbalance levels of a plurality of inductor currents of a plurality of channels of the multiphase DC-DC converter according to a plurality of current sensing signals of the plurality of channels;
a time shift circuit, for adjusting pulse widths of a plurality of clock signals according to the plurality of current balance signals; and
a ramp generator, for deciding shift levels of a plurality of ramp signals according to the plurality of clock signals;
wherein when one of the plurality of inductor currents is greater than an average inductor current of the plurality of inductor currents, the time shift circuit reduces a pulse width of a corresponding clock signal among the plurality of clock signals, and the ramp generator advances a time of starting to increase a voltage of a corresponding ramp signal among the plurality of ramp signals with a fixed slope; or
when one of the plurality of inductor currents is less than an average inductor current of the plurality of inductor currents, the time shift circuit increases a pulse width of a corresponding clock signal among the plurality of clock signals, and the ramp generator delays a time of starting to increase a voltage of a corresponding ramp signal among the plurality of ramp signals with a fixed slope.
2. The current balance circuit of claim 1 , wherein when the plurality of clock signals are at a higher voltage level, the ramp generator maintains the plurality of ramp signals at a predefined voltage level, and when the plurality of clock signals are at a lower voltage level, the ramp generator increases voltages of the plurality of ramp signals with a fixed slope.
3. The current balance circuit of claim 1 , wherein the multiphase DC-DC converter is voltage-controlled, and the ramp generator outputs the plurality of ramp signals to be compared with a voltage error signal, so as to generate a plurality of duty cycles.
4. The current balance circuit of claim 1 , wherein the multiphase DC-DC converter is current-controlled, and the ramp generator adds the plurality of ramp signals with the plurality of current sensing signals respectively to output a plurality of summation signals to be compared with a voltage error signal, so as to generate a plurality of duty cycles.
5. A multiphase DC-DC converter, comprising:
a plurality of channels, for outputting a plurality of inductor currents;
a current sensing circuit, for detecting magnitudes of the plurality of inductor currents, to generate a plurality of current sensing signals; and
a current balance circuit, comprising:
a current error calculation circuit, for generating a plurality of current balance signals indicating imbalance levels of the plurality of inductor currents according to the plurality of current sensing signals;
a time shift circuit, for adjusting pulse widths of a plurality of clock signals according to the plurality of current balance signals; and
a ramp generator, for deciding shift levels of a plurality of ramp signals according to the plurality of clock signals;
wherein when one of the plurality of inductor currents is greater than an average inductor current of the plurality of inductor currents, the time shift circuit reduces a pulse width of a corresponding clock signal among the plurality of clock signals, and the ramp generator advances a time of starting to increase a voltage of a corresponding ramp signal among the plurality of ramp signals with a fixed slope; or
when one of the plurality of inductor currents is less than an average inductor current of the plurality of inductor currents, the time shift circuit increases a pulse width of a corresponding clock signal among the plurality of clock signals, and the ramp generator delays a time of starting to increase a voltage of a corresponding ramp signal among the plurality of ramp signals with a fixed slope.
6. The multiphase DC-DC converter of claim 5 , wherein when the plurality of clock signals are at a higher voltage level, the ramp generator maintains the plurality of ramp signals at a predefined voltage level, and when the plurality of clock signals are at a lower voltage level, the ramp generator increases voltages of the plurality of ramp signals with a fixed slope.
7. The multiphase DC-DC converter of claim 5 , wherein the multiphase DC-DC converter is voltage-controlled, and the ramp generator outputs the plurality of ramp signals to be compared with a voltage error signal, so as to generate a plurality of duty cycles.
8. The multiphase DC-DC converter of claim 5 , wherein the multiphase DC-DC converter is current-controlled, and the ramp generator adds the plurality of ramp signals with the plurality of current sensing signals respectively to output a plurality of summation signals to be compared with a voltage error signal, so as to generate a plurality of duty cycles.
9. A current balance method for a multiphase DC-DC converter, comprising:
generating a plurality of current balance signals indicating imbalance levels of a plurality of inductor currents of a plurality of channels of the multiphase DC-DC converter according to a plurality of current sensing signals of the plurality of channels;
adjusting pulse widths of a plurality of clock signals according to the plurality of current balance signals; and
deciding shift levels of a plurality of ramp signals according to the plurality of clock signals;
wherein when one of the plurality of inductor currents is greater than an average inductor current of the plurality of inductor currents, reduce a pulse width of a corresponding clock signal among the plurality of clock signals, and advance a time of starting to increase a voltage of a corresponding ramp signal among the plurality of ramp signals with a fixed slope; or
when one of the plurality of inductor currents is less than an average inductor current of the plurality of inductor currents, increase a pulse width of a corresponding clock signal among the plurality of clock signals, and delay a time of starting to increase a voltage of a corresponding ramp signal among the plurality of ramp signals with a fixed slope.
10. The current balance method of claim 9 , wherein when the plurality of clock signals are at a higher voltage level, maintain the plurality of ramp signals at a predefined voltage level, and when the plurality of clock signals are at a lower voltage level, increase voltages of the plurality of ramp signals with a fixed slope.
11. The current balance method of claim 9 , further comprising outputting the plurality of ramp signals to be compared with a voltage error signal, so as to generate a plurality of duty cycles.
12. The current balance method of claim 9 , further comprising adding the plurality of ramp signals with the plurality of current sensing signals respectively to output a plurality of summation signals to be compared with a voltage error signal, so as to generate a plurality of duty cycles.