Multi-port static random-access memory (SRAM) with buffered read port and p and n pass gates to same write bit line
A multi-port memory cell has a write-only cell and a buffered read port. The write-only cell has cross-coupled inverters and transmission gates to write bit lines. Each transmission gate has n-channel and p-channel transistors in parallel that both turn on during writing but remain off for reading. A node in the cross-coupled inverters is applied to a gate of a buffer transistor that has a channel in series with a channel of a read pass transistor to a read bit line. The buffered read port can be an inverter and a transmission gate, or can have p-channel and n-channel buffer and pass transistors in a four-transistor stack. The number of p-channel and n-channel transistors can be equal for use in a standard-cell or macro library layout, and the standard-cell logic power supply can be used for the memory cells even for ultra-low supply voltages.
1 . A multi-port-cell memory comprising:
an array of memory cells, each memory cell comprising:
a first pull-up p-channel transistor having a source connected to a power supply, a drain connected to a first node, and a gate connected to a second node;
a first pull-down n-channel transistor having a source connected to a ground voltage supply, a drain connected to the first node, and a gate connected to the second node;
a second pull-up p-channel transistor having a source connected to the power supply, a drain connected to the second node, and a gate connected to the first node;
a second pull-down n-channel transistor having a source connected to the ground voltage supply, a drain connected to the second node, and a gate connected to the first node;
a first n-channel pass transistor having a gate connected to a write word line, and a channel connected between the first node and a first write bit line;
a second n-channel pass transistor having a gate connected to the write word line, and a channel connected between the second node and a second write bit line;
a first p-channel pass transistor having a gate connected to an inverse write word line, and a channel connected between the first node and the first write bit line;
a second p-channel pass transistor having a gate connected to the inverse write word line, and a channel connected between the second node and the second write bit line;
a read-port inverting p-channel transistor having a gate connected to the second node, a source connected to the power supply, and a drain connected to a first read-port node;
a read-port pass p-channel transistor having a gate connected to an inverse read word line, and a channel connected between the first read-port node and a read bit line;
a read-port inverting n-channel transistor having a gate connected to the second node, a source connected to the ground voltage supply, and a drain connected to a second read-port node; and
a read-port pass n-channel transistor having a gate connected to a read word line, and a channel connected between the second read-port node and the read bit line;
wherein each row in the array of memory cells has a write word line, an inverse write word line, a read word line, and an inverse read word line that connect to memory cells in a row;
wherein each column in the array of memory cells has a first write bit line, a second write bit line, and a read bit line that connect to memory cells in the column,
whereby the memory cell has four word lines and three bit lines;
wherein the power supply is a logic power supply that is also used by logic cells in a chip that includes the multi-port-cell memory;
wherein each row further comprises;
a write word line driver that drives the power supply onto the write word line when the row is selected and being written, and that connects the ground voltage supply to the write word line when the row is not selected and being written;
an inverse write word line driver that connects the ground voltage supply to the inverse write word line when the row is selected and being written, and that connects the power supply voltage to the inverse write word line when the row is not selected and being written;
a read word line driver that drives the power supply onto the read word line when the row is selected and being read, and that connects the ground voltage supply to the read word line when the row is not selected and being read;
an inverse read word line driver that connects the ground voltage supply to the inverse read word line when the row is selected and being read, and that connects the power supply voltage to the inverse read word line when the row is not selected and being read;
wherein each column further comprises:
a write bit line driver that connects the power supply to the first write bit line when an input data bit is high and writing is enabled, and that connects the ground voltage supply to the first write bit line when the input data bit is low and writing is enabled;
an inverse write bit line driver that connects the power supply to the second write bit line when the input data bit is low and writing is enabled, and that connects the ground voltage supply to the second write bit line when the input data bit is high and writing is enabled;
a read amplifier that generates an output data bit that is high when the read bit line is high during a read, and that generates the output data bit that is low when the read bit line is low during a read;
wherein the first write bit line and the second write bit line are not connected to the read amplifier and are not used for reading but only for writing;
a metal line that shorts together the first read-port node and the second read-port node;
wherein the read-port pass p-channel transistor and the read-port pass n-channel transistor comprise a transmission gate.
2 . A Static Random Access Memory (SRAM) cell comprising:
a write-only SRAM cell that comprises:
a first pull-up transistor and a first pull-down transistor connected in series between a power supply and a ground, the first pull-up transistor and the first pull-down transistor connected at a first latch node;
a second pull-up transistor and a second pull-down transistor connected in series between the power supply and the ground, the second pull-up transistor and the second pull-down transistor connected at a second latch node;
wherein gates of the first pull-up transistor and of the first pull-down transistor are driven by the second latch node between the second pull-up transistor and the second pull-down transistor;
wherein gates of the second pull-up transistor and of the second pull-down transistor are driven by the first latch node between the first pull-up transistor and the first pull-down transistor;
a first n-channel pass transistor connected between the first latch mode and a first write bit line, and having a gate connected to a write word line;
a second n-channel pass transistor connected between the second latch node and a second write bit line, and having a gate connected to the write word line;
a first p-channel pass transistor connected between the first latch node and the first write bit line, and having a gate connected to an inverse write word line;
a second p-channel pass transistor connected between the second latch node and the second write bit line, and having a gate connected to the inverse write word lines;
a buffered read port that comprises:
a buffer transistor with a gate connected to the second latch node from the write-only SRAM cell, and a channel that conducts current controlled by the gate; and
a pass transistor having a gate connected to a read word line and a channel connected between the channel of the buffer transistor and a read bit line;
wherein reading is performed by activating the read word line and sensing read data on the read bit line;
wherein writing is performed by activating the write word line high and the inverse write word line low and driving input data onto the first write bit line and driving an inverse of the input data onto the second write bit line;
wherein the buffered read port further comprises:
a p-channel buffer transistor with a gate connected to the second latch node from the write-only SRAM cell, and a channel that conducts current between the power supply and a first read-port node;
a p-channel pass transistor having a gate connected to an inverse read word line and a channel connected between first read-port node and the read bit line;
wherein the buffer transistor further comprises a n-channel buffer transistor with the gate connected to the second latch node from the write-only SRAM cell, and the channel that conducts current between the ground and a second read-port node;
wherein the pass transistor further comprises a n-channel pass transistor having the gate connected to the read word line and the channel connected between the second read-port node and the read bit line;
a metal line connected between the first read-port node and the second read-port node to short the first read-port node to the second read-port node;
wherein the p-channel pass transistor and the n-channel pass transistor comprise a transmission gate.