Processor, address translation, based on plurality of memory management units (MMUs), method and apparatus, storage medium, and program product
A plurality of physical cores of a processor share a memory management unit (MMU) pool comprising a plurality of MMUs. The plurality of MMUs provides each physical core with an address translation function from a virtual address (VA) to a physical address (PA). If an address translation requirement of a physical core is high, for example, when a main memory is concurrently accessed, the plurality of MMUs can serve the physical core.
1 . A processor, comprising:
an internal bus;
a memory management unit (MMU) pool comprising a plurality of MMUs; and
a plurality of physical cores connected, through the internal bus, to the MMU pool, wherein plurality of physical cores comprises a first physical core that is any one of the plurality of physical cores, and wherein the first physical core is configured to:
query, for a page table entry in which a to-be-translated first virtual address (VA) is located, a translation lookaside buffer (TLB) corresponding to the first physical core, wherein the page table entry comprises a mapping relationship between the to-be-translated first VA and a first physical address (PA);
send, to the MMU pool of the processor, an address translation request when the TLB does not cache the page table entry, wherein the address translation request carries the to-be-translated first VA; and
receive, from the MMU pool, an address translation response carrying the first PA corresponding to the to-be-translated first VA.
2 . The processor of claim 1 , wherein the MMU pool is further configured to provide an address translation function for the plurality of physical cores and a peripheral connected to the processor.
3 . The processor of claim 1 , wherein the MMU pool is located in a home agent (HA) of the processor.
4 . The processor of claim 1 , wherein the MMU pool is located in a memory controller (MC) of the processor.
5 . The processor of claim 1 , wherein the MMU pool is further configured to:
receive the address translation request;
translate the to-be-translated first VA into the first PA; and
send the address translation response to the first physical core.
6 . The processor of claim 5 , wherein the MMU pool is further configured to query a memory page table for the page table entry to obtain the first PA corresponding to the to-be-translated first VA, and wherein the memory page table records page table entries in which all VAs in a main memory are located.
7 . The processor of claim 6 , wherein the memory page table is a single-level page table.
8 . The processor of claim 6 , wherein the memory page table is a multi-level page table.
9 . The processor of claim 1 , wherein the processor is a general-purpose processing unit.
10 . The processor of claim 1 , wherein the processor is a network processor (NP).
11 . The processor of claim 1 , wherein the processor is an application-specific integrated circuit (ASIC).
12 . The processor of claim 1 , wherein the processor is a programmable logic device (PLD).
13 . The processor of claim 12 , wherein the PLD is a complex programmable logic device (CPLD).
14 . The processor of claim 12 , wherein the PLD is a field-programmable gate array FPGA).
15 . The processor of claim 12 , wherein the PLD is a generic array logic (GAL).
16 . A method, comprising:
querying, by a first physical core of a processor and for a page table entry in which a to-be-translated first virtual address (VA) is located, a translation lookaside buffer (TLB) corresponding to the first physical core, wherein the page table entry comprises a mapping relationship between the to-be-translated first VA and a first physical address (PA);
the TLB does not cache the page table entry;
sending, by the first physical core of the processor and to a memory management unit (MMU) pool of the processor, an address translation request in response to the TLB does not cache the page table entry, wherein the MMU pool comprises a plurality of MMUs, wherein the address translation request carries the to-be-translated first VA, and wherein the first physical core is any one of a plurality of physical cores of the processor; and
receiving, by the first physical core and from the MMU pool, an address translation response carrying the first PA corresponding to the to-be-translated first VA.
17 . A method, comprising:
a translation lookaside buffer (TLB), corresponding to a first physical core of a processor, does not cache a page table entry comprising a mapping relationship between a to-be-translated first virtual address (VA) and a first physical address (PA), wherein a memory management unit (MMU) pool comprises a plurality of MMUs, wherein an address translation request carries the to-be-translated first VA, and wherein the first physical core is any one of a plurality of physical cores of the processor;
receiving, by the MMU pool of the processor and from the first physical core, the address translation request in response to the TLB does not cache the page table entry;
translating, by the MMU pool, the to-be-translated first VA into the first PA; and
sending, by the MMU pool and to the first physical core, an address translation response carrying the first PA corresponding to the to-be-translated first VA.
18 . The method of claim 17 , wherein translating the to-be-translated first VA into the first PA comprises querying, by the MMU pool and for the page table entry in which the to-be-translated first VA is located, a memory page table to obtain the first PA corresponding to the to-be-translated first VA, and wherein the memory page table records page table entries in which all VAs in a main memory are located.
19 . The method of claim 17 , wherein the plurality of MMUs correspond to one management module, and wherein translating, the to-be-translated first VA into the first PA comprises:
selecting, by the MMU pool, from the plurality of MMUs, and by using the management module, one MMU as a target MMU; and
translating, by the MMU pool and by using the target MMU, the to-be-translated first VA into the first PA.
20 . The method of claim 17 , further comprising querying, by the MMU pool, a memory page table for the page table entry to obtain the first PA corresponding to the to-be-translated first VA, wherein the memory page table records page table entries in which all VAs in a main memory are located.