IP Library › Granted Patent US 12,592,734
Granted Patent B2
US 12,592,734 · App. 18/705,931 · Granted Mar 31, 2026

Low noise block-downconverter system with local oscillator module

Inventors: Serguei Khoudiakov (Hope, CA); Alexei Gouterman (Richmond, CA); Mehdi Rezvani Abkenari (Coquitlam, CA)
Assignee: Orbital Research Ltd.
H04B1/18H03L7/099
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,592,734
App. No.
18/705,931
Granted
Mar 31, 2026
Kind
B2
Abstract

A low noise block-downconverter system (LNB system) includes a local oscillator module having first and second phase locked loop circuitry (PLL circuitry) for downconverting an electrical signal to generate a downconverted signal. The first PLL circuitry receives a low-frequency reference signal that is used with an intermediate-frequency oscillator to generate an intermediate-frequency signal. The second PLL circuitry receives and uses the intermediate-frequency signal in conjunction with a high-frequency oscillator, separate from the intermediate-frequency oscillator, to generate a high-frequency signal. The high-frequency signal is used to downconvert the electrical signal. The signal dynamic range of the first PLL circuitry is higher than the signal dynamic range of the second PLL circuitry, thus achieving improved overall dynamic range for the LNB system. The first PLL circuitry may be a first integrated circuit defining a low phase-noise amplifier. A second integrated circuit may include the second PLL circuitry and the high-frequency oscillator.

Claims (38)

1 . A low noise block-downconverter system (LNB system), comprising:

a local oscillator module configured to generate a high-frequency signal for downconversion, and including

first phase locked loop circuitry (first PLL circuitry) configured to receive a low-frequency reference signal and connected in feedback to an intermediate-frequency oscillator so as to control the intermediate-frequency oscillator to generate an intermediate-frequency signal based on the low-frequency reference signal,

second phase locked loop circuitry (second PLL circuitry) configured to receive the intermediate-frequency signal and connected in feedback to a high-frequency oscillator, separate from the intermediate-frequency oscillator, so as to control the high-frequency oscillator to generate the high-frequency signal based on the intermediate-frequency signal, a signal dynamic range of the first PLL circuitry being higher than the signal dynamic range of the second PLL circuitry; and

low noise processing circuitry configured to receive an electrical signal generated by a probe in response to a radio frequency signal, the low noise processing circuitry configured to process the electrical signal using the high-frequency signal to generate a downconverted signal suitable for output from the LNB system.

2 . The LNB system of claim 1 , wherein the first PLL circuitry is an integrated circuit defining at least one low noise amplifier suitable for enhancing signal dynamic range of the first PLL circuitry.

3 . The LNB system of claim 2 , wherein the at least one low noise amplifier includes a low phase noise amplifier configured to process the low-frequency reference signal to generate an amplified signal for a phase detector of the first PLL circuitry.

4 . The LNB system of claim 1 , wherein an integrated circuit defines, in combination, the second PLL circuitry and the high-frequency oscillator.

5 . The LNB system of claim 4 , wherein the integrated circuit is a second integrated circuit, and the first PLL circuitry is a first integrated circuit defining at least one low phase noise amplifier suitable for enhancing signal dynamic range of the first PLL circuitry, the intermediate-frequency oscillator being externally connected to the first integrated circuit.

6 . The LNB system of claim 4 , wherein the intermediate-frequency oscillator is a crystal oscillator.

7 . The LNB system of claim 6 , wherein the intermediate-frequency oscillator is an oven-controlled crystal oscillator or a temperature-controlled crystal oscillator.

8 . The LNB system of claim 6 , further comprising:

a chassis for mounting the local oscillator module and the low noise processing circuitry in the LNB system;

a temperature sensor positioned to generate an indicator of chassis temperature;

a power supply connected to the local oscillator module and the low noise processing circuitry to power the local oscillator module to generate the high-frequency signal and to power the low noise processing circuitry to generate the downconverted signal; and

a circuit connected to the temperature sensor and the power supply, the circuit being configured to control the power supply to vary power supplied to the local oscillator module based on the indicator to vary thermal energy dissipated by the first PLL circuitry and the second PLL circuitry to control the chassis temperature and to provide heating around the crystal oscillator.

9 . The LNB system of claim 1 , wherein the intermediate-frequency oscillator is suitable for oscillating at at least one intermediate frequency between 10 MHz and 100 MHz and the low-frequency reference signal is suitable for oscillating at at least one low frequency below 10 MHz.

10 . The LNB system of claim 1 , wherein the first PLL circuitry is an integrated circuit externally connected to a low-pass filter, the low-pass filter connected to the intermediate-frequency oscillator.

11 . The LNB system of claim 1 , wherein an integrated circuit defines, in combination, the second PLL circuitry and the high-frequency oscillator, the integrated circuit externally connected to a low-pass filter.

12 . The LNB system of claim 1 , further comprising:

a chassis for mounting the local oscillator module and the low noise processing circuitry in the LNB system, the local oscillator module and the low noise processing circuitry disposed on opposing sides of the chassis; and

a transverse printed circuit board (transverse PCB) extending across the chassis between the opposing sides to connect the local oscillator module to the low noise processing circuitry.

13 . A method of operating a low noise block-downconverter system (LNB system), comprising:

receiving a low-frequency reference signal in first phase locked loop circuitry (first PLL circuitry) defining a first signal dynamic range and being connected in feedback to an intermediate-frequency oscillator;

controlling the intermediate-frequency oscillator, using the first PLL circuitry, based on the low-frequency reference signal to generate an intermediate-frequency signal;

receiving the intermediate-frequency signal in second phase locked loop circuitry (second PLL circuitry) defining a second signal dynamic range smaller than the first signal dynamic range and being connected in feedback to a high-frequency oscillator;

controlling the high-frequency oscillator, using the second PLL circuitry, based on the intermediate-frequency signal to generate a high-frequency signal;

generating an electrical signal in response to a radio frequency signal; and

processing the electrical signal using the high-frequency signal to generate a downconverted signal suitable for output from the LNB system.

14 . The method of claim 13 , further comprising:

amplifying the low-frequency reference signal using a low phase noise amplifier of the first PLL circuitry to generate an amplified signal for a phase detector of the first PLL circuitry.

15 . The method of claim 13 , wherein the first PLL circuitry is a first integrated circuit externally connected to the intermediate-frequency oscillator, and a second integrated circuit defines, in combination, the second PLL circuitry and the high-frequency oscillator.

16 . The method of claim 15 , wherein the intermediate-frequency oscillator is an oven-controlled crystal oscillator or a temperature-controlled crystal oscillator.

17 . A printed circuit board assembly (PCB assembly) defining a local oscillator module for a low noise block-downconverter system (LNB system), comprising:

first phase locked loop circuitry (first PLL circuitry) configured to receive a low-frequency reference signal and connected in feedback to an intermediate-frequency oscillator so as to control the intermediate-frequency oscillator to generate an intermediate-frequency signal based on the low-frequency reference signal; and

second phase locked loop circuitry (second PLL circuitry) configured to receive the intermediate-frequency signal and connected in feedback to a high-frequency oscillator, separate from the intermediate-frequency oscillator, so as to control the high-frequency oscillator to generate a high-frequency signal based on the intermediate-frequency signal, a signal dynamic range of the first PLL circuitry being higher than the signal dynamic range of the second PLL circuitry, the high-frequency signal being suitable for use in low noise processing circuitry of the LNB system to downconvert an electrical signal indicative of a radio frequency signal to generate a downconverted signal.

18 . The PCB assembly of claim 17 , wherein the first PLL circuitry is a first integrated circuit defining at least one low phase noise amplifier suitable for enhancing signal dynamic range of the first PLL circuitry, and a second integrated circuit defines, in combination, the second PLL circuitry and the high-frequency oscillator.

19 . The PCB assembly of claim 18 , wherein the intermediate-frequency oscillator is an oven-controlled crystal oscillator or a temperature-controlled crystal oscillator.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2024
From: KHOUDIAKOV, SERGUEI; GOUTERMAN, ALEXEI; ABKENARI, MEHDI REZVANI
To: ORBITAL RESEARCH LTD.
Reel/Frame 067258/0891 →
Continuity (2)
Provisional Application 63274933 · Nov 2, 2021
Related Publication 20250007552A1 · Jan 2, 2025
References Cited (95)
US 5448255A · Hulett · 1995 [cited by examiner]
US 5507025A · Rodeffer · 1996 [cited by examiner]
US 6424817B1 · Hadden · 2002 [cited by examiner]
US 6968020B1 · Jayaraman · 2005 [cited by examiner]
US 7079400B2 · Inamoto · 2006 [cited by examiner]
US 7082169B2 · Rozenblit · 2006 [cited by examiner]
US 7091759B2 · Sowlati · 2006 [cited by examiner]
US 7138839B2 · Zachan · 2006 [cited by examiner]
US 7256629B2 · Zachan · 2007 [cited by examiner]
US 7319850B2 · Motoyama · 2008 [cited by examiner]
US 7355463B2 · Sowlati · 2008 [cited by examiner]
US 7564928B2 · Jayaraman · 2009 [cited by examiner]
US 7576614B2 · Zachan · 2009 [cited by examiner]
US 8102196B1 · Zhang · 2012 [cited by applicant]
US 8351796B2 · Wang · 2013 [cited by examiner]
US 8355470B1 · Mason · 2013 [cited by examiner]
US 8725104B2 · Ling · 2014 [cited by examiner]
US 8818319B2 · Alderton · 2014 [cited by examiner]
US 9042851B2 · Ling · 2015 [cited by examiner]
US 9571885B2 · Ling · 2017 [cited by examiner]
US 9859926B2 · Shah · 2018 [cited by examiner]
US 9893743B2 · Adamski · 2018 [cited by examiner]
US 10153790B2 · Shah · 2018 [cited by examiner]
US 10244283B2 · Ling · 2019 [cited by examiner]
US 10326689B2 · Liu · 2019 [cited by examiner]
US 10374558B1 · Kuo · 2019 [cited by examiner]
US 10439575B1 · Kuo · 2019 [cited by examiner]
US 10541742B1 · Andrade · 2020 [cited by examiner]
US 11923962B2 · Blatt · 2024 [cited by examiner]
US 12132512B2 · Huang · 2024 [cited by examiner]
US 20030083034A1 · Motoyama · 2003 [cited by examiner]
US 20040017858A1 · Rozenblit · 2004 [cited by examiner]
US 20050258907A1 · Zachan · 2005 [cited by examiner]
US 20050264369A1 · Sowlati · 2005 [cited by examiner]
US 20060158235A1 · Zachan · 2006 [cited by examiner]
US 20060208778A1 · Sowlati · 2006 [cited by examiner]
US 20070247200A1 · Zachan · 2007 [cited by examiner]
US 20110283330A1 · Wang · 2011 [cited by examiner]
US 20130293322A1 · Alderton · 2013 [cited by examiner]
US 20170302302A1 · Adamski · 2017 [cited by examiner]
US 20220311508A1 · Kim · 2022 [cited by examiner]
US 20230283317A1 · Huang · 2023 [cited by examiner]
US 20230291466A1 · Blatt · 2023 [cited by examiner]
US 20250007552A1 · Khoudiakov · 2025 [cited by examiner]
AU 2021359855A1 · 2023 [cited by examiner]
AU 2021359855A9 · 2024 [cited by examiner]
BR 112023007074B1 · 2025 [cited by examiner]
CA 3100605A1 · 2019 [cited by examiner]
CA 3100605C · 2023 [cited by examiner]
CA 3236663A1 · 2023 [cited by examiner]
CN 1220059A · 1999 [cited by examiner]
CN 1361943A · 2002 [cited by examiner]
CN 1105417C · 2003 [cited by examiner]
CN 1210866C · 2005 [cited by examiner]
CN 2792022Y · 2006 [cited by examiner]
CN 101137020A · 2008 [cited by examiner]
CN 102255659A · 2011 [cited by examiner]
CN 202221995U · 2012 [cited by examiner]
CN 202308251U · 2012 [cited by examiner]
CN 202455340U · 2012 [cited by examiner]
CN 103001585A · 2013 [cited by examiner]
CN 102625062B · 2014 [cited by examiner]
EP 0523770A1 · 1993 [cited by examiner]
EP 0860965A2 · 1998 [cited by applicant]
EP 0523770B1 · 1999 [cited by examiner]
EP 3163776A1 · 2017 [cited by examiner]
EP 3236600A1 · 2017 [cited by examiner]
EP 4218158B1 · 2025 [cited by examiner]
FR 3018971A1 · 2015 [cited by examiner]
GB 2540002A · 2017 [cited by applicant]
JP 2004159283A · 2004 [cited by examiner]
JP 2013258622A · 2013 [cited by examiner]
KR 20180107012A · 2018 [cited by examiner]
KR 20210011022A · 2021 [cited by examiner]
KR 20240152919A · 2024 [cited by examiner]
TW M261921U · 2005 [cited by examiner]
TW I407718B · 2013 [cited by examiner]
TW 201412051A · 2014 [cited by examiner]
TW I594596B · 2017 [cited by examiner]
TW 202007094A · 2020 [cited by examiner]
WO WO9512953A1 · 1995 [cited by examiner]
WO WO2005117264A2 · 2005 [cited by examiner]
WO WO2019226694A1 · 2019 [cited by examiner]
WO WO2022082026A1 · 2022 [cited by examiner]
WO WO2022212255A1 · 2022 [cited by examiner]
WO WO2023077226A2 · 2023 [cited by examiner]
WO WO2023166385A1 · 2023 [cited by examiner]
C. Vaucher and D. Kasperkovitz, “A wide band tuning system for fully integrated satellite receivers,” Proceedings of the 23rd European Solid-State Circuits Conference, Southampton, UK, 1997, pp. 56-59. (Year: 1997). [cited by examiner]
A. Maxim, M. Gheorghe and C. Turinici, “Notice of Violation of IEEE Publication Principles: 9.75/10.6GHz SiGe PLL for LNB Satellite Front-Ends Using Half-Rate Oscillators,” 2006 Symposium on VLSI Circuits, 2006. Digest … [cited by examiner]
Voucher Cicero, Architecture for RF Frequency Synthesizers, Kluwer Academic Publishers, 2002-2003 (Year: 2002). [cited by examiner]
Vaucher C et al.: “A wide band tuning system for fully integrated satellite receivers”, Solid-State Circuits Conference, 1997. ESSCIRC '97. Proceedings of the 23rd European, IEEE, Sep. 16, 1997 (Sep. 16, 1997), pp. 56-5… [cited by applicant]
Johan D Van Der Tang et al.: “A Low-Phase-Noise Reference Oscillator with Integrated pMOS Varactors for Digital Satellite Receivers”, IEEE Journal of Solid-State Circuits, IEEE, USA, vol. 35, No. 8, Aug. 1, 2000 (Aug. 1… [cited by applicant]
Friis H T: “Noise Figures of Radio Receivers”, Jul. 31, 1944 (Jul. 31, 1944), pp. 419-422, XP093276049, Proceedings of the IRE ( vol. 32, Issue: 7, Jul. 1944) DOI: 10.1109/JRPROC.1944.232049, Retrieved from the Internet… [cited by applicant]
Anonymous: “Friis formulas for noise—Wikipedia”, Jan. 20, 2018 (Jan. 20, 2018), pp. 1-2, XP093276050, Retrieved from the Internet: URL:https://en.wikipedia.org/w/index.php?title=Friis_formulas_for_noise&oldid=821487487. [cited by applicant]
Ul Haq Zia et al.: “A novel dual PLL if block for on-board LEO satellite receivers”, 2017 Fifth International Conference On Aerospace Science & Engineering (ICASE), IEEE, Nov. 14, 2017 (Nov. 14, 2017), pp. 1-5, XP033354… [cited by applicant]