Loop filter integration in phase-locked loops
A phase-locked loop and method of operation are disclosed. One embodiment includes providing a phase-locked loop, comprising a charge pump system comprising a first charge pump and a second charge pump, the charge pump system configured to provide control signals, a dual path filter, the dual path filter consisting of passive components that are configured to provide summation of control signals, wherein the dual path filter includes a first node coupled between a first charge pump and a first capacitor, wherein the dual path filter includes a second node coupled to a second charge pump through a first resistor, wherein the second node is connected to the first capacitor, and a voltage source coupled to the second node through a second resistor.
1. A semi-conductor chip, comprising:
a phase-locked loop including:
a charge pump system comprising a first charge pump and a second charge pump configured to provide control signals comprising a first control signal and a second control signal, respectively, wherein the first control signal increases or decreases in magnitude concurrently with the second control signal;
a dual path filter, the dual path filter consisting of passive components that are configured in a defined ratio to provide summation of the control signals, wherein the dual path filter includes a first node coupled between the first charge pump and a first capacitor, wherein the dual oath filter includes a second node coupled to the second charge pump through a first resistor, wherein the second node is connected to the first capacitor; and
a voltage source coupled to the second node through a second resistor.
2. The chip of claim 1 , wherein the dual path filter includes an integrator coupled to a low-pass filter.
3. The chip of claim 1 , wherein the dual path filter is integrated with the phase-locked loop on the chip.
4. The chip of claim 1 , wherein the passive components are configured to provide at least one of a low-frequency zero and a high-frequency pole.
5. A phase-locked loop, comprising:
a charge pump system comprising a first charge pump and a second charge pump, the charge pump system configured to provide control signals;
a dual path filter, the dual path filter consisting of passive components that are configured to provide summation of the control signals, wherein the dual path filter includes a first node coupled between a first charge pump and a first capacitor, wherein the dual path filter includes a second node coupled to a second charge pump through a first resistor, wherein the second node is connected to the first capacitor; and
a voltage source coupled to the second node through a second resistor.
6. The phase-locked loop of claim 5 , further including a third node coupled between the voltage source and the second resistor.
7. The phase-locked loop of claim 6 , further including a second capacitor coupled between the first capacitor and the third node.
8. The phase-locked loop of claim 7 , further including a third capacitor coupled between ground and the first resistor.
9. The phase-locked loop of claim 5 , further including an oscillator coupled to a single output connection corresponding to the loop filter, the single output connection configured to carry the summed control signals.
10. The phase-locked loop of claim 5 , further including a phrase-frequency detector coupled to the charge pump system.
11. The phase-locked loop of claim 5 , further including a divide-by-N module receptive to an output signal from the oscillator, wherein N is a fractional number or an integer number.
12. The phase-locked loop of claim 5 , further including a mixer receptive to an output signal from the oscillator.
13. A transceiver, comprising:
a phase-locked loop, comprising:
a charge pump system comprising a first charge pump and a second charge pump, the charge pump system configured to provide control signals;
a dual path filter, the dual path filter consisting of passive components that are configured to provide summation of the control signals, wherein the dual path filter includes a first node coupled between a first charge pump and a first capacitor, wherein the dual path filter includes a second node coupled to a second charge pump through a first resistor, wherein the second node is connected to the first capacitor; and
a voltage source coupled to the second node through a second resistor.
14. The transceiver of claim 13 , further including a third node coupled between the voltage source and the second resistor.
15. The transceiver of claim 14 , further including a second capacitor coupled between the first capacitor and the third node.
16. The transceiver of claim 15 , further including a third capacitor coupled between ground and the first resistor.
17. The transceiver of claim 13 , further including an oscillator coupled to a single output connection corresponding to the loop filter, the single output connection configured to carry the summed control signals.
18. The transceiver of claim 13 , further including a phrase-frequency detector coupled to the charge pump system.
19. The transceiver of claim 13 , further including a divide-by-N module receptive to an output signal from the oscillator, wherein N is a fractional number or an integer number.
20. The transceiver of claim 13 , further including a mixer receptive to an output signal from the oscillator.