Apparatus and methods for negative threshold voltages for nonvolatile memory devices

1 . A method of operating a memory device, comprising the steps of:

preparing a memory device that includes a memory block with an array of memory cells that are arranged in a plurality of word lines;

programming the memory cells of a selected word line of the plurality of word lines according to a one bit per memory cell (SLC) storage scheme that includes an erased data state and a programmed data state; and

wherein both the memory cells in the erased data state and the memory cells in the programmed data state have threshold voltages that are less than 0 V.

2 . The method as set forth in claim 1 , further including the steps of:

applying a reference voltage to the selected word line and applying a read pass voltage to a plurality of unselected word lines of the plurality of word lines;

performing a sensing operation to compare a threshold voltage of a selected memory cell of the selected word line to the reference voltage; and

wherein the read pass voltage is no greater than 0.5 V.

3 . The method as set forth in claim 2 , wherein the read pass voltage is no greater than 0 V.

4 . The method as set forth in claim 2 , wherein the step of applying the reference voltage to the selected word line includes ramping the selected word line down from approximately 0 V to the reference voltage, which is less than 0 V.

5 . The method as set forth in claim 2 , wherein the reference voltage is less than the read pass voltage.

6 . The method as set forth in claim 1 , wherein both the memory cells in the erased data state and the memory cells in the programmed data state have threshold voltages that are less than −1 V.

7 . The method as set forth in claim 1 , wherein the step of programming the memory cells of the selected word line includes a plurality of program loops with programming pulses and verify operations,

wherein during the verify operations, a verify voltage is applied to the selected word line, and

wherein the verify voltage is less than 0 V.

8 . A memory device, comprising:

a memory block with an array of memory cells that are arranged in a plurality of word lines; and

the memory cells being programmed according to a one bit per memory cell (SLC) programming scheme that includes an erased data state and a programmed data state, and wherein the memory cells in both the erased data state and in the programmed data state have threshold voltages that are less than 0 V.

9 . The memory device as set forth in claim 8 , further including circuitry that is configured to read the memory cells of a selected word line of the plurality of word lines, and wherein while reading the memory cells of the selected word line, the circuitry is configured to:

apply a reference voltage to the selected word line and apply a read pass voltage to a plurality of unselected word lines of the plurality of word lines, and

wherein the read pass voltage is no greater than 0.5 V.

10 . The memory device as set forth in claim 9 , wherein the read pass voltage is no greater than 0 V.

11 . The memory device as set forth in claim 9 , wherein before applying the reference voltage to the selected word line, the circuitry is configured to ramp down the selected word line from approximately 0 V to the reference voltage, and wherein the reference voltage is less than 0 V.

12 . The memory device as set forth in claim 9 , wherein the reference voltage is less than the read pass voltage.

13 . The memory device as set forth in claim 8 , wherein the memory cells in both the erased data state and the programmed data state have threshold voltages that are less than −1 V.

14 . The memory device as set forth in claim 8 , further including circuitry that is configured to program the memory cells of the memory block in a plurality of program loops, each program loop including a programming pulse and a verify operation, and wherein a verify voltage that is used during the verify operation is less than 0 V.

15 . A computing system, comprising:

a processor unit;

a plurality of high bandwidth flash (HBF) packages in electrical communication with the processor unit;

at least one of the HBF packages including a memory block with an array of memory cells that are arranged in a plurality of word lines, the memory cells being programmed according to a one bit per memory cell (SLC) programming scheme that includes an erased data state and a programmed data state, and wherein the memory cells in both the erased data state and in the programmed data state have threshold voltages that are less than 0 V.

16 . The computing system as set forth in claim 15 , further including circuitry that is configured to read the memory cells of a selected word line of the plurality of word lines, and wherein while reading the memory cells of the selected word line, the circuitry is configured to:

apply a reference voltage to the selected word line and apply a read pass voltage to a plurality of unselected word lines of the plurality of word lines, and

wherein the read pass voltage is no greater than 0.5 V.

17 . The computing system as set forth in claim 16 , wherein the read pass voltage is no greater than 0 V.

18 . The computing system as set forth in claim 16 , wherein before applying the reference voltage to the selected word line, the circuitry is configured to ramp down the selected word line from approximately 0 V to the reference voltage, and wherein the reference voltage is less than 0 V.

19 . The computing system as set forth in claim 16 , wherein the reference voltage is less than the read pass voltage.

20 . The computing system as set forth in claim 16 , wherein the memory cells in both the erased data state and the programmed data state have threshold voltages that are less than −1 V.