Granted Patent B2

US 12,744,096 · App. 18/735,986 · Granted Sep 22, 2026

Inventor: Seunghan Lee (Suwon-si, KR)

Assignee: SAMSUNG ELECTRONICS CO., LTD.

G11C16/349G11C16/08G11C16/102G11C16/32

Abstract

Claims (47)

1 . A storage device comprising:

a NAND flash memory device configured to receive a command and an address for a write operation or an erase operation via command-address pins, transmit and receive write data or read data via data pins, and generate degeneration information indicating at least one of a program execution time required to perform the write operation and an erase execution time required to perform the erase operation; and

a storage controller configured to receive the degeneration information from the NAND flash memory device, and control the NAND flash memory device to adjust at least one of a program voltage of the write operation and an erase voltage of the erase operation based on the degeneration information,

wherein the storage controller is configured to adjust the program voltage to a first voltage level based on the program execution time indicated by the degeneration information being within a first interval, and adjust the program voltage to a second voltage level different from the first voltage level based on the program execution time indicated by the degeneration information being within a second interval different from the first interval.

2 . The storage device of claim 1 , wherein the NAND flash memory device is further configured to transmit the degeneration information to the storage controller via the command-address pins.

3 . The storage device of claim 1 , wherein the storage controller is further configured to control the NAND flash memory device to decrease the program voltage based on the degeneration information indicating a decrease in the program execution time.

4 . The storage device of claim 1 , wherein the storage controller is further configured to control the NAND flash memory device to increase the erase voltage based on the degeneration information indicating an increase in the erase execution time.

5 . The storage device of claim 1 , wherein the NAND flash memory device is further configured to update the degeneration information by measuring the program execution time and the erase execution time each time a program-erase count reaches any of a plurality of reference counts.

6 . The storage device of claim 1 , wherein the NAND flash memory device is further configured to update the degeneration information by measuring the program execution time and the erase execution time based on a request from the storage controller.

7 . The storage device of claim 1 , wherein the NAND flash memory device is further configured to provide, to the storage controller, a state signal that is activated at a first logic level indicating a ready state while in the ready state and deactivated at a second logic level indicating a busy state while performing internal operations for the write operation or the erase operation, and

wherein the NAND flash memory device is further configured to measure the program execution time or the erase execution time based on a time interval while the state signal is deactivated to the second logic level during the write operation or the erase operation.

8 . The storage device of claim 7 , wherein the NAND flash memory device is further configured to receive the command and the address in synchronization with a command-address clock signal provided from the storage controller, and

wherein the NAND flash memory device is further configured to measure the program execution time by counting clock cycles of the command-address clock signal while the state signal is deactivated to the second logic level during the write operation.

9 . The storage device of claim 1 , wherein the NAND flash memory device is further configured to operate according to Separate Command Address (SCA) protocol.

10 . The storage device of claim 1 , wherein the nonvolatile NAND flash memory device is further configured to set at least one target wordline among wordlines of a memory block and measure the program execution time with respect to the at least one target wordline.

11 . The storage device of claim 1 , wherein the NAND flash memory device is further configured to measure the program execution time with respect to each of a plurality of wordlines of a memory block to obtain a plurality of program execution times, and control the program voltage with respect to the memory block based on an average value of the plurality of program execution times.

12 . The storage device of claim 1 , wherein the NAND flash memory device is further configured to:

perform the write operation in accordance with incremental step pulse programming (ISPP);

incrementally increase the program voltage as a program loop is repeated; and

measure the program execution time based on a number of program loops performed to complete the write operation.

13 . The storage device of claim 1 , wherein the NAND flash memory device is further configured to:

perform the erase operation in accordance with an incremental step pulse erasing (ISPE),

increase the erase voltage step by step as an erase loop is repeated; and

measure the erase execution time based on a number of erase loops performed to complete the erase operation.

14 . The storage device of claim 1 , wherein the NAND flash memory device is further configured to:

perform the write operation in accordance with incremental step pulse programming (ISPP);

incrementally increase the program voltage as a program loop is repeated; and

decrease the program voltage of a first program loop of the ISPP based on the degeneration information indicating an increased degree of degeneration of the NAND flash memory device.

15 . The storage device of claim 1 , wherein the NAND flash memory device is further configured to perform the erase operation in accordance with an incremental step pulse erasing (ISPE), and incrementally increase the erase voltage step by step as an erase loop is repeated, and

wherein the storage controller is further configured to control the NAND flash memory device to increase the erase voltage of a first erase loop of the ISPE based on the degeneration information indicating an increased degree of degeneration of the NAND flash memory device.

16 . A method of operating a storage device including a NAND flash memory device and a storage controller configured to control the NAND flash memory device, comprising:

generating degeneration information indicating at least one of a program execution time required to perform a write operation and an erase execution time required to perform an erase operation of the NAND flash memory device;

providing the degeneration information from the NAND flash memory device to the storage controller; and

controlling the NAND flash memory device to adjust at least one of a program voltage of the write operation and an erase voltage of the erase operation based on the degeneration information,

wherein the controlling the NAND flash memory device comprises adjusting the program voltage to a first voltage level based on the program execution time indicated by the degeneration information being within a first interval, and adjusting the program voltage to a second voltage level different from the first voltage level based on the program execution time indicated by the degeneration information being within a second interval different from the first interval.

17 . The method of claim 16 , wherein the generating the degeneration information comprises:

generating a state signal that is activated at a first logic level indicating a ready state while in the ready state and deactivated at a second logic level indicating a busy state while performing internal operations for the write operation or the erase operation; and

measuring the program execution time or the erase execution time based on a time interval while the state signal is deactivated to the second logic level during the write operation or the erase operation.

18 . The method of claim 16 , wherein controlling the NAND flash memory device comprises controlling the NAND flash memory device to decrease the program voltage based on the degeneration information indicating a decrease in the program execution time.

19 . The method of claim 16 , wherein controlling the NAND flash memory device comprises controlling the NAND flash memory device to increase the erase voltage based on the degeneration information indicating an increase in the erase execution time.

20 . A NAND flash memory device comprising:

a memory cell array comprising a plurality of nonvolatile memory cells;

command-address pins configured to communicate a command and an address for a write operation or an erase operation;

data pins configured to communicate write data and readout data;

a state pin configured to communicate a state signal that is activated at a first logic level indicating a ready state while in the ready state and deactivated at a second logic level indicating a busy state while performing internal operations for the write operation or the erase operation; and

a degeneration detector circuit configured to generate degeneration information indicating at least one of a program execution time to perform the write operation and an erase execution time to perform the erase operation, based on the state signal,

wherein the NAND flash memory device is configured to adjust a program voltage to a first voltage level based on the program execution time indicated by the degeneration information being within a first interval, and adjust the program voltage to a second voltage level different from the first voltage level based on the program execution time indicated by the degeneration information being within a second interval different from the first interval.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (16)