Semiconductor memory device and memory system

1. A semiconductor memory device comprising:

a memory cell array having a plurality of memory cell groups, each of which includes a plurality of memory cells, the memory cell groups including a first memory group including first memory cells and a second memory group including second memory cells;

a first word line that is connected to each of the first memory cells;

a second word line that is connected to each of the second memory cells; and

a control circuit configured to execute a first write operation targeting the first memory cells in a first mode in which the control circuit executes at least a first programming operation on the first memory cells followed by a multiple number of first verification operations to verify the first programming operation, and then in a second mode, in which the control circuit executes a second programming operation on the first memory cells followed by a second verification operation to verify the second programming operation, wherein

a programming voltage applied to the first word line during the second programming operation is less than a programming voltage applied to the first word line during the first programming operation, and is adjusted based on a number of first verification operations.

2. The semiconductor memory device according to claim 1 , wherein

the programming voltage applied to the first word line during the second programming operation is adjusted further based on a number of first programming operations executed during the first mode.

3. The semiconductor memory device according to claim 2 , wherein

the programming voltage applied to the first word line during the second programming operation is a first voltage when the number of first programming operations is N1 and the number of first verification operations is N2, and a second voltage when the number of first programming operations is N1 and the number of first verification operations is N3, and

the first voltage is greater than the second voltage if N2<N3, and less than the second voltage if N2>N3.

4. The semiconductor memory device according to claim 2 , wherein

the programming voltage applied to the first word line during the second programming operation is a third voltage when the number of first programming operations is N4 and the number of first verification operations is N5, and a fourth voltage when the number of first programming operations is N6 and the number of first verification operations is N5, and

the first voltage is greater than the second voltage if N4>N6, and less than the second voltage if N4<N6.

5. The semiconductor memory device according to claim 1 , wherein the control circuit is configured to:

execute a second write instruction, which is the next write instruction after the first write instruction, in accordance with whether or not the second write operation targets the first memory cells.

6. The semiconductor memory device according to claim 5 , wherein the control circuit is configured to:

if the second write operation does not target the first memory cells, execute the second write instruction in the first mode, and then in the second mode.

7. The semiconductor memory device according to claim 5 , wherein the control circuit is configured to:

store the programming voltage applied to the first word line during the second programming operation, and

if the second write operation targets the first memory cells, execute the second write instruction in a third mode, in which the control circuit executes a third programming operation on the first memory cells followed by a third verification operation to verify the third programming operation, wherein

a programming voltage applied to the first word line during the third programming operation is the same as the stored programming voltage.

8. The semiconductor memory device according to claim 1 , wherein the control circuit is configured to:

execute a second write instruction, which is the next write instruction after the first write instruction, in accordance with whether or not the second write operation targets memory cells that are connected to the first word line or a different word lines that is in a same zone of word lines as the first word line.

9. The semiconductor memory device according to claim 1 , wherein the control circuit is configured to:

execute a second write instruction, which is the next write instruction after the first write instruction, in accordance with whether or not the second write operation targets memory cells that are in a same block as the first memory cells.

10. The semiconductor memory device according to claim 1 , wherein the control circuit is configured to:

execute a second write instruction, which is the next write instruction after the first write instruction, in accordance with whether or not the second write operation targets memory cells that has a same row address as the first memory cells.

11. The semiconductor memory device according to claim 1 , wherein the control circuit is configured to:

execute a second write instruction, which is the next write instruction after the first write instruction, in accordance with whether or not the second write operation targets memory cells that have been rewritten a number of times in excess of a threshold number of rewrites.

12. A semiconductor memory device comprising:

a memory cell array having a plurality of memory cell groups, each of which includes a plurality of memory cells that are connected to a common word line; and

a control circuit configured to execute consecutive first and second write operations by

executing at least a first programming operation on memory cells targeted by the first write operation followed by a multiple number of first verification operations to verify the first programming operation,

executing a second programming operation on the memory cells targeted by the first write operation followed by a second verification operation to verify the second programming operation,

storing the programming voltage applied during the second programming operation, to a word line connected to the memory cells targeted by the first write operation, and

executing the second write operation in accordance with whether or not the second write operation meets a condition for using the stored programming voltage.

13. The semiconductor memory device according to claim 12 , wherein

a programming voltage applied during the second programming operation is less than a programming voltage applied during the first programming operation, and is adjusted based on a number of first verification operations.

14. The semiconductor memory device according to claim 13 , wherein

upon determining that the second write operation does meet the condition for using the stored programming voltage, executing a third programming operation on memory cells targeted by the second write operation followed by a third verification operation to verify the third programming operation, and

a programming voltage used during the third programming operation is the same as the stored programming voltage.

15. The semiconductor memory device according to claim 13 , wherein

upon determining that the second write operation does not meet the condition for using the stored programming voltage,

executing at least a third programming operation on memory cells targeted by the second write operation followed by a multiple number of third verification operations to verify the third programming operation, and

executing a fourth programming operation on the memory cells targeted by the second write operation followed by a fourth verification operation to verify the second programming operation.

16. The semiconductor memory device according to claim 12 , wherein the condition is one of:

memory cells targeted by the second write operation is the same as the memory cells targeted by the first write operation;

a word line connected to the memory cells targeted by the second write operation is the same as a word line connected to the memory cells targeted by the first write operation;

a word line connected to the memory cells targeted by the second write operation is in a same zone as a word line connected to the memory cells targeted by the first write operation;

a row address of the memory cells targeted by the second write operation is the same as a row address of the memory cells targeted by the first write operation; and

a number of rewrites performed on the memory cells targeted by the second write operation is less than a threshold number of rewrites.

17. A method of performing a write operation on a group of memory cells of a semiconductor memory device that are connected to a common word line, comprising:

(a) executing at least a first programming operation on the memory cells followed by a multiple number of first verification operations to verify the first programming operation;

(b) executing a second programming operation on the memory cells followed by a second verification operation to verify the second programming operation;

(c) storing the programming voltage applied during the second programming operation, to the word line connected to the memory cells; and

(d) upon completion of a first write operation that includes steps (a), (b), and (c), executing a next write operation in accordance with whether or not a second write operation meets a condition for using the stored programming voltage.

18. The method according to claim 17 , wherein

a programming voltage applied during the second programming operation is less than a programming voltage applied during the first programming operation, and is adjusted based on a number of first verification operations.

19. The method according to claim 18 , further comprising:

upon determining that the second write operation does meet the condition for using the stored programming voltage, executing a third programming operation on memory cells targeted by the second write operation followed by a third verification operation to verify the third programming operation, and

a programming voltage used during the third programming operation is the same as the stored programming voltage.

20. The method according to claim 18 , wherein

upon determining that the second write operation does not meet the condition for using the stored programming voltage,

executing at least a third programming operation on memory cells targeted by the second write operation followed by a multiple number of third verification operations to verify the third programming operation, and

executing a fourth programming operation on the memory cells targeted by the second write operation followed by a fourth verification operation to verify the fourth programming operation.