Transistor device with tapered gate contact profile
A device includes a source region and a drain region over a substrate. The device further includes a gate structure at least partially between the source region and the drain region, and a gate contact over the gate structure. The gate contact has an upper portion and a lower portion below the upper portion. The lower portion is more tapered than the upper portion.
1 . A device, comprising:
a source region over a substrate;
a drain region over the substrate and spaced apart from the source region;
a gate structure at least partially between the source region and the drain region; and
a gate contact over the gate structure, the gate contact having an upper portion and a lower portion below the upper portion, the lower portion being more tapered than the upper portion, wherein the upper portion of the gate contact has a substantially vertical sidewall, and the lower portion of the gate contact has an inclined sidewall extending from the substantially vertical sidewall, wherein the substantially vertical sidewall is in contact with the inclined sidewall of the lower portion, wherein a height of the lower portion of the gate contact is less than a height of the upper portion of the gate contact.
2 . The device of claim 1 , wherein the lower portion of the gate contact has a width increasing as a distance from the gate structure increases.
3 . The device of claim 1 , wherein the upper portion of the gate contact has a width remaining substantially constant as a distance from the gate structure increases.
4 . The device of claim 1 , further comprising:
a first dielectric layer interfacing the lower portion of the gate contact; and
a second dielectric layer interfacing the upper portion of the gate contact.
5 . The device of claim 4 , wherein the second dielectric layer has a greater impurity concentration than the first dielectric layer.
6 . The device of claim 4 , wherein the second dielectric layer has a thinner thickness than the first dielectric layer.
7 . The device of claim 4 , wherein the second dielectric layer is entirely above the lower portion of the gate contact.
8 . The device of claim 4 , wherein the substantially vertical sidewall and the inclined sidewall meet at a bottom surface of the second dielectric layer.
9 . The device of claim 1 , The device of claim 1 , further comprising:
an interlayer dielectric (ILD) layer over the gate structure, wherein the upper portion of the gate contact extends through the ILD layer.
10 . A device, comprising:
a gate structure over a substrate;
a first doped semiconductor region at a first side of the gate structure;
a second doped semiconductor region at a second side of the gate structure;
a first dielectric region over the gate structure;
a second dielectric region over the first dielectric region, the second dielectric region having a higher impurity concentration than the first dielectric region; and
a gate contact extending through the first dielectric region and the second dielectric region to electrically connect with the gate structure, wherein the gate contact has a first portion below an interface between the first dielectric region and the second dielectric region, and a second portion above the interface between the first dielectric region and the second dielectric region, wherein a width of the first portion changes at a greater rate along a vertical direction than the second portion, wherein a sidewall of the gate contact has a slope change at the interface formed by a top surface of the first dielectric region and a bottom surface of the second dielectric region.
11 . The device of claim 10 , wherein the width of the first portion of the gate contact decreases as a distance from the second portion of the gate contact increases.
12 . The device of claim 10 , wherein a width of the second portion remains substantially constant along the vertical direction.
13 . The device of claim 10 , wherein the impurity concentration of the second dielectric region is an oxygen concentration.
14 . The device of claim 10 , wherein the first dielectric region has a maximal thickness greater than a maximal thickness of the second dielectric region.
15 . The device of claim 10 , wherein the second portion of the gate contact has a topmost surface higher than a topmost surface of the second dielectric region.
16 . The device of claim 10 , wherein the first dielectric region has a non-linear bottom surface.
17 . A device, comprising:
a gate conductor over a substrate;
a first gate spacer over a first sidewall of the gate conductor;
a second gate spacer over a second sidewall of the gate conductor;
a first dielectric over a top surface of the gate conductor;
a second dielectric having a bottom surface in contact with a top surface of the first dielectric, the second dielectric being different from the first dielectric at least in an impurity concentration; and
a gate contact extending through the first dielectric and the second dielectric to electrically connect with the gate conductor, wherein a sidewall of the gate contact exhibits a change in slope at an interface formed by the top surface of the first dielectric and the bottom surface of the second dielectric.
18 . The device of claim 17 , wherein the sidewall of the gate contact comprises a first portion extending substantially vertically above the interface between the first dielectric and the second dielectric.
19 . The device of claim 18 , wherein the sidewall of the gate contact further comprises a second portion angled from the first portion, wherein the first portion of the gate contact extends a height greater than a height of the second portion.
20 . The device of claim 17 , wherein the gate conductor comprises a first metal and a second metal spacing apart the first metal from the gate contact.