Method, system and computer program product for memory repair
It is checked, using machine learning, whether at least one fail bit in a memory block of a memory is unrepairable, according to a location of the at least one fail bit, and an available repair resource in the memory. When the checking indicates that the at least one fail bit is not unrepairable, it is determined whether a CSP containing constraints is solvable. The constraints correspond to the location of the at least one fail bit in the memory block, and the available repair resource. In response to determining that the CSP is not solvable, the memory block is marked as unrepairable or the memory is rejected. In response to the checking, using the machine learning, indicating that the at least one fail bit is unrepairable, the memory block is marked as unrepairable or the memory is rejected, without making further determinations as to repairability of the memory block.
1 . A method, said method executed at least partially by a processor, comprising:
extracting, from at least one memory test on a memory block of a memory,
a location of at least one fail bit to be repaired in the memory block, and
a location of at least one weak bit in the memory block;
obtaining an available repair resource in the memory for repairing the memory block; and
controlling allocation of the available repair resource to repair the memory block, wherein
the allocation of the available repair resource to repair the at least one fail bit is controlled based on a plurality of constraints and a first objective function, the plurality of constraints corresponding to the location of the at least one fail bit in the memory block and the available repair resource, and
the allocation of the available repair resource to repair the at least one weak bit is controlled based on the plurality of constraints and a second objective function different from the first objective function.
2 . The method of claim 1 , wherein
the first objective function comprises minimizing an amount of the available repair resource allocated to repair the at least one fail bit.
3 . The method of claim 1 , wherein
the plurality of constraints comprises:
∑
i
=
1
m
x
i
≥
m
-
x
repair
resource
,
∑
j
=
1
n
y
j
≥
n
-
y
repair
resource
,
and
∑
k
=
1
h
(
x
i
_
k
·
y
j
_
k
)
=
0
,
where m is a number of word lines in the memory block,
n is a number of bit lines in the memory block,
h is a number of fail bits to be repaired in the memory block,
x repair resource is a number of redundant word lines available to repair the memory block,
y repair resource is a number of redundant bit lines available to repair the memory block,
x i is either 0 or 1 and corresponds to an i th word line among the m word lines, x i =0 corresponding to the i th word line being repaired by one of the redundant word lines, and x i =1 corresponding to the i th word line not being repaired,
y j is either 0 or 1 and corresponds to a j th bit line among the n bit lines, y j =0 corresponding to the j th bit line being repaired by one of the redundant bit lines, and y j =1 corresponding to the j th bit line not being repaired,
x i_k is x i corresponding to the word line coupled to a k th fail bit among the h fail bits, and
y j_k is y j corresponding to the bit line coupled to the k th fail bit.
4 . The method of claim 3 , wherein
the first objective function comprises maximizing
∑
i
=
1
m
x
i
and
∑
j
=
1
n
y
j
.
5 . The method of claim 1 , wherein:
the at least one weak bit comprises a plurality of weak bits including a first weak bit and a second weak bit, and
the second objective function comprises allocating the available repair resource to preferentially repair the first weak bit with a higher weakness level over the second weak bit with a lower weakness level.
6 . The method of claim 5 , said method further comprising:
assigning a plurality of different weights to the plurality of weak bits, the different weights corresponding to different weakness levels of the plurality of weak bits.
7 . The method of claim 6 , wherein
the plurality of constraints comprises:
∑
i
=
1
m
x
i
≥
m
-
x
repair
resource
,
∑
j
=
1
n
y
j
≥
n
-
y
repair
resource
,
and
∑
k
=
1
h
(
x
i
_
k
·
y
j
_
k
)
=
0
,
and
the second objective function comprises
minimizing
∑
l
=
1
s
W
l
(
x
l
·
y
l
)
,
where m is a number of word lines in the memory block,
n is a number of bit lines in the memory block,
h is a number of fail bits to be repaired in the memory block,
s is a number of weak bits in the memory block,
x repair resource is a number of redundant word lines available to repair the memory block,
y repair resource is a number of redundant bit lines available to repair the memory block,
x i is either 0 or 1 and corresponds to an i th word line among the m word lines, x i =0 corresponding to the i th word line being repaired by one of the redundant word lines, and x i =1 corresponding to the i th word line not being repaired,
y j is either 0 or 1 and corresponds to a j th bit line among the n bit lines, y j =0 corresponding to the j th bit line being repaired by one of the redundant bit lines, and y j =1 corresponding to the j th bit line not being repaired,
x′ i is either 0 or 1 and corresponds to an i′ th redundant word line, x′ i′ =0 corresponding to the i′ th redundant word line not being used to repair a word line, and x′ i′ =1 corresponding to the i′ th redundant word line being used to repair a word line,
y′ j′ is either 0 or 1 and corresponds to a j′ th redundant bit line, y′ j′ =0 corresponding to the j′ th redundant bit line not being used to repair a bit line, and y′ j′ =1 corresponding to the j′ th redundant bit line being used to repair a bit line,
x i is x i or x′ i′ corresponding to the word line or redundant word line coupled to an l th weak bit among the s weak bits,
y l is y j or y′ j′ corresponding to the bit line or redundant bit line coupled to the l th weak bit, and
W i is the weight assigned to the l th weak bit.
8 . A system, comprising:
a memory testing device configured to perform at least one memory test on a memory block of a memory; and
a processor coupled to the memory testing device,
wherein the processor is configured to
extract, from the at least one memory test, a location of at least one fail bit to be repaired in the memory block,
obtain an available repair resource in the memory for repairing the memory block,
determine, using first machine learning, whether the at least one fail bit is unrepairable according to
the location of the at least one fail bit in the memory block, and
the available repair resource, and
in response to determining, using the first machine learning, that the at least one fail bit is not unrepairable, determine whether a Constraint Satisfaction Problem (CSP) containing a plurality of constraints is solvable, the plurality of constraints corresponding to
the location of the at least one fail bit in the memory block, and
the available repair resource,
in response to determining that the CSP is not solvable, control the memory testing device to mark the memory block as unrepairable or to reject the memory, and
in response to determining that the CSP is solvable, update a heuristic of the CSP using second machine learning separate from the first machine learning.
9 . The system of claim 8 , further comprising a database, wherein
the processor is further configured to, in response to determining that the CSP is solvable, add information related to the heuristic of the CSP to the database.
10 . The system of claim 9 , wherein
the database contains information related to a plurality of heuristics is supplied from multiple systems for memory testing and repairing, and
the processor is configured to perform the second machine learning to select an optimal heuristic among the plurality of heuristics.
11 . A computer program product, comprising a non-transitory, computer-readable medium containing therein instructions executable by a processor to cause the processor to
extract a location of at least one fail bit to be repaired in a memory block of a memory,
obtain an available repair resource in the memory for repairing the memory block,
determine whether the at least one fail bit is repairable according to
the location of the at least one fail bit in the memory block, and
the available repair resource,
in response to determining that the at least one fail bit is repairable, determine whether a remaining repair resource exists upon allocating at least a part of the available repair resource to repair the at least one fail bit, and
in response to determining that the remaining repair resource exists, control a memory testing device to perform at least one memory test on the memory block by
applying same test data to the memory block in multiple runs of the at least one memory test at corresponding different testing conditions, and
determining a location of at least one weak bit in the memory block from results of the multiple runs of the at least one memory test.
12 . The computer program product of claim 11 , wherein the instructions are executable by the processor to further cause the processor to
in response to determining that the at least one fail bit is unrepairable,
control the memory testing device to mark the memory block as unrepairable or to reject the memory, without performing a memory test on the memory block to extract a location of a weak bit in the memory block.
13 . The computer program product of claim 11 , wherein
the different testing conditions comprise different write voltages supplied from the memory testing device to the memory block to write the test data in the corresponding multiple runs of the at least one memory test.
14 . The computer program product of claim 11 , wherein
the at least one weak bit comprises:
a first weak bit exhibiting an error in
a first run, among the multiple runs, at a corresponding first testing condition, and
a second run, among the multiple runs, at a corresponding second testing condition tighter than the first testing condition, and
a second weak bit exhibiting an error in the second run, but not in the first run, and
the instructions are executable by the processor to further cause the processor to
assign different weights to the first weak bit and the second weak bit, and
based on the different weights assigned to the first weak bit and the second weak bit, control repairing at least one of the first weak bit or the second weak bit.
15 . The computer program product of claim 14 , wherein the instructions are executable by the processor to cause the processor to
formulate an objective function of a Constraint Optimization Problem (COP) based on the different weights and locations of the first weak bit and the second weak bit,
control repairing the memory block based on a solution of the COP, wherein
the COP contains a plurality of constraints and the objective function, and
the solution of the COP satisfies the plurality of constraints, optimizes the objective function, and indicates how the available repair resource in the memory is allocated in a repair of the at least one fail bit and the at least one of the first weak bit or the second weak bit.
16 . The computer program product of claim 11 , wherein
the at least one weak bit comprises a plurality of weak bits,
the instructions are executable by the processor to further cause the processor to
assign a plurality of different weights to the plurality of weak bits, the different weights corresponding to different weakness levels of the plurality of weak bits, and
based on locations of and the plurality of different weights assigned to the plurality of weak bits, control a repair of the at least one fail bit and one or more weak bits among the plurality of weak bits.
17 . The computer program product of claim 16 , wherein
the plurality of weak bits includes at least one first weak bit in the available repair resource in the memory, and
the instructions are executable by the processor to further cause the processor to
assign, among the plurality of different weights, at least one weight, which corresponds to a weakness level of the at least one first weak bit in the available repair resource in the memory, to the at least one first weak bit in the available repair resource in the memory, and
based on the locations of and the plurality of different weights assigned to the plurality of weak bits including the at least one first weak bit in the available repair resource, control the repair of the at least one fail bit and the one or more weak bits among the plurality of weak bits.
18 . The computer program product of claim 17 , wherein the instructions are executable by the processor to cause the processor to
control the repair of the at least one fail bit and the one or more weak bits among the plurality of weak bits, by allocating, from the available repair resource, a redundant bit line or word line not including the at least one first weak bit to the repair, before allocating a redundant bit line or word line including the at least one first weak bit.
19 . The method of claim 1 , wherein
the available repair resource comprises a plurality of redundant lines each of which is a redundant bit line or a redundant word line,
the at least one weak bit comprises a plurality of weak bits including a first weak bit in a first redundant line among the plurality of redundant lines, and
the second objective function comprises allocating, among the plurality of redundant lines, a redundant line not including any weak bit among the plurality of weak bits, before allocating the first redundant line including the first weak bit, to repair the memory block.
20 . The method of claim 1 , further comprising:
in response to determining that any fail bit of the at least one fail bit is unrepairable, marking the memory block as unrepairable or rejecting the memory; and
in response to determining that any weak bit of the at least one weak bit remains unrepaired, finishing repair of the memory block, without marking the memory block as unrepairable or rejecting the memory.