PROGRAMMING WITHOUT PRE-CHARGE IN NONVOLATILE MEMORY DEVICES
The memory device includes a memory block with an array of memory cells that are arranged in a plurality of word lines and memory holes. The memory device also includes circuitry for programming the memory cells of a selected word line of the plurality of word lines to a single bit per memory cell format. The circuitry is configured to, in a first program loop, apply a programming pulse to the selected word line and then conduct a verify operation. Then, without pre-charging the memory holes after the verify operation of the first program loop, in a second program loop, the circuitry is configured to apply a programming pulse to the selected word line and then conduct a verify operation.
1 . A method of operating a memory device, comprising the steps of:
preparing a memory block that includes an array of memory cells that are arranged in a plurality of word lines and memory holes;
in a first program loop to program the memory cells of a selected word line to a single bit per memory cell format, applying a programming pulse to the selected word line and then conducting a verify operation; and
without pre-charging the memory holes after the first program loop, in a second program loop, applying a programming pulse to the selected word line and then conducting a verify operation.
2 . The method as set forth in claim 1 , wherein between the first and second program loops, a programming voltage is increased by a step size, and wherein the step size is no greater than 0.2 V.
3 . The method as set forth in claim 1 , wherein programming continues through a plurality of program loops until the verify operation passes or until the programming voltage reaches a predetermined maximum programming voltage.
4 . The method as set forth in claim 3 , wherein the predetermined maximum programming voltage is no greater than 17 V.
5 . The method as set forth in claim 3 , wherein after the verify operation passes, all of the memory cells of the selected word line have threshold voltages below 2 V.
6 . The method as set forth in claim 5 , wherein after the verify operation passes, the data has a threshold voltage window of no greater than 0.5 V.
7 . The method as set forth in claim 1 , wherein during the programming pulse of each of the program loops, a pass voltage is applied to a plurality of unselected word lines of the plurality of word lines.
8 . A memory device, comprising:
a memory block that includes an array of memory cells that are arranged in a plurality of word lines and memory holes;
circuitry for programming the memory cells of a selected word line of the plurality of word lines to a single bit per memory cell format, the circuitry being configured to;
in a first program loop, apply a programming pulse to the selected word line and then conduct a verify operation; and
without pre-charging the memory holes after the verify operation of the first program loop, in a second program loop, apply a programming pulse to the selected word line and then conduct a verify operation.
9 . The memory device as set forth in claim 8 , wherein between the first and second program loops, the circuitry increases a programming voltage by a step size that is no greater than 0.2 V.
10 . The memory device as set forth in claim 8 , wherein programming continues through a plurality of program loops until the verify operation passes or until the programming voltage reaches a predetermined maximum programming voltage.
11 . The memory device as set forth in claim 10 , wherein the predetermined maximum programming voltage is no greater than 17 V.
12 . The memory device as set forth in claim 11 , wherein after the verify operation passes, all of the memory cells of the selected word line have threshold voltages below 2 V.
13 . The memory device as set forth in claim 12 , wherein after the verify operation passes, the data has a threshold voltage window of no greater than 0.5 V.
14 . The memory device as set forth in claim 8 , wherein during the programming pulse of each of the program loops, the circuitry applies a pass voltage to a plurality of unselected word lines of the plurality of word lines.
15 . A computing system, comprising:
a processor unit;
a plurality of non-volatile memory packages in electrical communication with the processor unit, each of the non-volatile memory packages having a memory block that includes an array of memory cells that are arranged in a plurality of word lines and memory holes and having circuitry for programming the memory cells of a selected word line of the plurality of word lines to a single bit per memory cell format, the circuitry being configured to;
in a first program loop, apply a programming pulse to the selected word line and then conduct a verify operation; and
without pre-charging the memory holes after the verify operation of the first program loop, in a second program loop, apply a programming pulse to the selected word line and then conduct a verify operation.
16 . The computing system as set forth in claim 15 , wherein between the first and second program loops, the circuitry increases a programming voltage by a step size that is no greater than 0.2 V.
17 . The computing system as set forth in claim 15 , wherein programming continues through a plurality of program loops until the verify operation passes or until the programming voltage reaches a predetermined maximum programming voltage.
18 . The computing system as set forth in claim 17 , wherein the predetermined maximum programming voltage is no greater than 17 V.
19 . The computing system as set forth in claim 18 , wherein after the verify operation passes, all of the memory cells of the selected word line have threshold voltages below 2 V.
20 . The computing system as set forth in claim 17 , wherein after the verify operation passes, the data has a threshold voltage window of no greater than 0.5 V.