Integrated circuit devices including lower interconnect metal layers at cell boundaries and methods of forming the same
Integrated circuit devices are provided. An integrated circuit device includes a substrate and a cell that has a plurality of transistors. The transistors include an upper transistor having an upper channel region. Moreover, the transistors include a lower transistor between the substrate and the upper transistor. The lower transistor includes a lower channel region. The integrated circuit device includes a power line extending longitudinally in a first horizontal direction below the substrate and defining a cell boundary of the cell that extends longitudinally in the first horizontal direction. The integrated circuit device includes a cell boundary signal metal pattern on the cell and extending longitudinally in the first horizontal direction over the cell boundary and connected to at least two transistors of the plurality of transistors. Related methods of forming integrated circuit devices are also provided.
1 . An integrated circuit device comprising:
a substrate;
a cell comprising a plurality of transistors, the plurality of transistors including an upper transistor comprising an upper channel region, and the plurality of transistors including a lower transistor between the substrate and the upper transistor, the lower transistor comprising a lower channel region;
a power line extending longitudinally in a first horizontal direction below the substrate and defining a cell boundary of the cell that extends longitudinally in the first horizontal direction; and
a cell boundary signal metal pattern on the cell and extending longitudinally in the first horizontal direction over the cell boundary and connected to at least two transistors of the plurality of transistors,
wherein the power line is a first power line and the cell boundary defined thereby is a first cell boundary of the cell, the integrated circuit device further comprising a second power line extending longitudinally in the first horizontal direction parallel to the first power line, the second power line defining a second cell boundary of the cell that extends longitudinally in the first horizontal direction, and
wherein the first power line and the second power line are configured to carry a power signal having a same supply voltage.
2 . The integrated circuit device of claim 1 , further comprising:
a back-end-of-line (BEOL) structure comprising a plurality of metal layers on the cell, wherein the cell boundary signal metal pattern is in a first metal layer of the plurality of metal layers that is closest to the substrate.
3 . The integrated circuit device of claim 1 , wherein the cell boundary signal metal pattern is arranged along a cell boundary metal track that extends longitudinally over the cell boundary, the integrated circuit device further comprising a plurality of lower interconnection metal tracks that extend in parallel with the cell boundary signal metal pattern in the first horizontal direction and are spaced apart from each other and from the cell boundary in a second horizontal direction that intersects the first horizontal direction.
4 . The integrated circuit device of claim 1 , further comprising a third power line extending horizontally in the first horizontal direction and spaced apart in the second horizontal direction between the first and second power lines, the third power line configured to carry a power signal having a different supply voltage than the first power line.
5 . The integrated circuit device of claim 1 , wherein the integrated circuit device comprises a plurality of cells and the cell is a first cell of the plurality of cells, the further comprising a block routing metal pattern on the first cell and extending longitudinally in the first horizontal direction over the second cell boundary, the block routing metal pattern connected between a transistor of the first cell and another cell of the integrated circuit device.
6 . The integrated circuit device of claim 1 , wherein the upper transistor or the lower transistor is electrically connected to the power line by way of a via that extends through the substrate.
7 . An integrated circuit device comprising:
a cell comprising a plurality of transistors arranged on a first side of a substrate, the plurality of transistors including an upper transistor comprising an upper source/drain region, and the plurality of transistors including a lower transistor between the substrate and the upper transistor, the lower transistor comprising a lower source/drain region;
a back-end-of-line (BEOL) structure comprising a plurality of metal layers on the first side of the substrate, the upper transistor and lower transistor between a lowermost metal layer of the plurality of metal layers and the substrate; and
first and second power lines extending longitudinally in a first horizontal direction in parallel on a second side the substrate, the first power line and the second power line defining respectively a first cell boundary and a second cell boundary of the cell,
wherein the lowermost metal layer comprises a cell boundary signal metal pattern that extends longitudinally in the first horizontal direction over the first cell boundary and is connected to at least two transistors of the plurality of transistors, and
wherein the first and second power lines are configured to provide a same supply voltage to the cell.
8 . The integrated circuit device of claim 7 , wherein the cell boundary signal metal pattern is arranged along a first cell boundary metal track that extends longitudinally over the first cell boundary.
9 . The integrated circuit device of claim 8 , wherein the cell is a first cell, the integrated circuit device further comprising a block routing metal signal that is arranged along a second cell boundary metal track that extends longitudinally over the second cell boundary and is connected to a second cell of the integrated circuit device.
10 . The integrated circuit device of claim 7 , wherein the cell boundary signal metal pattern is electrically connected to the upper source/drain region.
11 . The integrated circuit device of claim 7 , wherein the cell boundary signal metal pattern is electrically connected to the lower source/drain region.
12 . The integrated circuit device of claim 7 , further comprising a third power line extending horizontally in the first horizontal direction and spaced apart in a second horizontal direction between the first and second power lines, the second horizontal direction intersecting the first horizontal direction, the third power line configured to carry a power signal having a different supply voltage than the first power line.
13 . The integrated circuit device of claim 7 , wherein the lower transistor is a N-type metal-oxide semiconductor field effect transistor (NMOSFET), and the upper transistor is a P-type metal-oxide semiconductor field effect transistor (PMOSFET).
14 . A method of forming an integrated circuit device, the method comprising:
forming a cell on a substrate, the cell comprising a plurality of transistors including a lower transistor and an upper transistor on the substrate, the lower transistor comprising a lower channel region and the upper transistor comprising an upper channel region, and the cell comprising a cell boundary that extends in a first horizontal direction;
forming a cell boundary metal pattern in a first metal layer above the substrate, the cell boundary metal pattern extending in the first horizontal direction and overlapping the cell boundary in a vertical direction, and the cell boundary metal pattern interconnecting at least two transistors of the plurality of transistors, the cell boundary metal pattern connected to at least one of the lower transistor and upper transistor; and
forming a power line extending longitudinally in the first horizontal direction, the cell boundary metal pattern overlapping the power line and the cell boundary in the vertical direction,
wherein the power line is a first power line and the cell boundary is a first cell boundary of the cell, the method further comprising forming a second power line extending longitudinally in the first horizontal direction parallel to the first power line, the second power line overlapping a second cell boundary of the cell that extends longitudinally in the first horizontal direction and spaced apart from the first cell boundary in a second horizontal direction that intersects the first horizontal direction, and
wherein the first power line and the second power line are configured to carry a power signal having a same supply voltage.
15 . The method of claim 14 , wherein the cell boundary metal pattern is electrically connected to an upper source/drain region of the upper transistor.
16 . The method of claim 14 , wherein the cell boundary metal pattern is electrically connected to a lower source/drain region of the lower transistor.