APPARATUS AND METHODS FOR AMPLIFIER CIRCUITS FOR READING MRAM MEMORY CELLS
An apparatus includes a memory cell including a magnetic memory element coupled in series with a selector element, the memory cell including a first terminal coupled to a word line driver circuit and a second terminal coupled to a bit line driver circuit, and an amplifier circuit comprising an input terminal coupled to the bit line driver circuit, and an output terminal coupled to a current source configured to conduct a read current. The amplifier circuit is configured to amplify a voltage that is based on a difference between a first voltage across the memory cell and a second voltage across the memory cell.
1 . An apparatus comprising:
a memory cell comprising a magnetic memory element coupled in series with a selector element, the memory cell comprising a first terminal coupled to a word line driver circuit and a second terminal coupled to a bit line driver circuit; and
an amplifier circuit comprising an input terminal coupled to the bit line driver circuit, and an output terminal coupled to a current source configured to conduct a read current,
wherein the amplifier circuit is configured to amplify a voltage that is based on a voltage across the memory cell.
2 . The apparatus of claim 1 , wherein the amplifier circuit comprises a common gate amplifier.
3 . The apparatus of claim 1 , wherein the amplifier circuit comprises a transistor comprising a first terminal coupled to the output terminal of the amplifier circuit, a second terminal coupled to the input terminal of the amplifier circuit, and a third terminal coupled to a power supply voltage.
4 . The apparatus of claim 1 , wherein the amplifier circuit comprises a transistor comprising a drain terminal comprising the output terminal of the amplifier circuit, a source terminal comprising the input terminal of the amplifier circuit, and a gate terminal coupled to a power supply voltage.
5 . The apparatus of claim 1 , wherein the amplifier circuit comprises a p-channel transistor configured to operate in a saturation region of operation.
6 . The apparatus of claim 1 , wherein the current source comprises a current mirror.
7 . The apparatus of claim 1 , further comprising a sense amplifier circuit comprising an input terminal coupled to the output terminal of the amplifier circuit.
8 . The apparatus of claim 7 , wherein the sense amplifier circuit is configured to compare a signal at the input terminal of the sense amplifier circuit with a reference voltage to determine a memory state of the memory cell.
9 . The apparatus of claim 1 , wherein the magnetic memory element is configured to switch between a first resistance state and a second resistance state.
10 . The apparatus of claim 1 , wherein:
the magnetic memory element conducts the read current;
the first voltage comprises a voltage drop across the magnetic memory element in a first resistance state; and
the second voltage comprises a voltage drop across the magnetic memory element in a second resistance state.
11 . The apparatus of claim 1 , wherein the selector element comprises an ovonic threshold switch.
12 . The apparatus of claim 1 , further comprising a cross-point memory array comprising the memory cell.
13 . An apparatus comprising:
a memory cell comprising a magnetic memory element coupled in series with an ovonic threshold switch, the memory cell comprising a first terminal coupled to a word line, and a second coupled to a bit line; and
a voltage regulator circuit comprising an output terminal coupled to the bit line, and an input terminal coupled to a second power supply voltage, the voltage regulator circuit configured to provide a lower limit on a voltage of the bit line,
wherein voltage regulator circuit amplifies a voltage that is based on a voltage across the memory cell.
14 . The apparatus of claim 13 , wherein the voltage regulator circuit comprises a source follower transistor.
15 . The apparatus of claim 13 , wherein the voltage regulator circuit comprises a common gate amplifier.
16 . The apparatus of claim 13 , wherein the voltage regulator circuit comprises a p-channel transistor configured to operate in a saturation region of operation.
17 . The apparatus of claim 1 , further comprising a sense amplifier circuit comprising an input terminal coupled to a third terminal of the voltage regulator circuit.
18 . The apparatus of claim 17 , wherein the sense amplifier circuit is configured to compare a signal at the input terminal of the sense amplifier circuit with a reference voltage to determine a memory state of the memory cell.
19 . The apparatus of claim 13 , wherein the magnetic memory element is configured to switch between a first resistance state and a second resistance state.
20 . A method comprising:
providing a memory cell comprising a magnetic memory element coupled in series with an ovonic threshold switch, the memory cell comprising a first terminal coupled to a word line, and a second terminal coupled to a bit line;
coupling the word line to a first power supply voltage;
coupling a source terminal of a p-channel transistor to the bit line;
coupling a gate terminal of the p-channel transistor to a second power supply voltage;
coupling a drain terminal of the p-channel transistor to a current mirror transistor and an input terminal of a sense amplifier; and
operating the p-channel transistor as a common gate amplifier to amplify a voltage at the input terminal of a sense amplifier, which voltage is based on a voltage across the memory cell.