Pixel circuit and display device including the same
A pixel circuit and a display device including the same are discussed. The pixel circuit in one example includes a driving element having a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node, a first capacitor connected between the second node and a fourth node, a second capacitor connected between the third node and the fourth node, a light emitting element including an anode electrode connected to a fifth node and a cathode electrode to which a cathode voltage is applied, a first switch element configured to connect a data voltage to the second node, and a switch circuit configured to selectively apply a reference voltage to the second node and the fourth node.
1 . A pixel circuit comprising:
a driving element including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node;
a first capacitor connected between the second node and a fourth node;
a second capacitor connected between the third node and the fourth node;
a light emitting element including an anode electrode connected to a fifth node and a cathode electrode to which a cathode voltage is applied;
a first switch element configured to apply a data voltage to the second node; and
a switch circuit configured to selectively apply a reference voltage to the second node and the fourth node, the switch circuit including at least two transistors connected in series between the reference voltage and one of the second node and the fourth node.
2 . The pixel circuit of claim 1 , wherein the switch circuit includes:
a second switch element configured to apply the reference voltage to a sixth node in response to a second gate signal;
a third switch element configured to electrically connect the sixth node to the fourth node in response to the second gate signal; and
a fourth switch element configured to electrically connect the sixth node to the second node in response to a third gate signal,
wherein the first switch element is turned on or off in response to a first gate signal.
3 . The pixel circuit of claim 2 , wherein
a driving period of the pixel circuit includes a first period, a second period, a third period, a fourth period, and a fifth period,
a voltage of the first gate signal is a gate-on voltage during the third period and a gate-off voltage during the first, second, fourth, and fifth periods,
a voltage of the second gate signal is the gate-on voltage during the first, second, and third periods and the gate-off voltage during the fourth and fifth periods,
a voltage of the third gate signal is the gate-on voltage during the first, second, and fourth periods and the gate-off voltage during the third and fifth periods, and
each of the first switch element, the second switch element, the third switch element, and the fourth switch element is turned on in response to the gate-on voltage and is turned off in response to the gate-off voltage.
4 . The pixel circuit of claim 2 , wherein
the first switch element includes a first electrode connected to a data line to which the data voltage is applied, a gate electrode to which the first gate signal is applied, and a second electrode connected to the second node,
the second switch element includes a first electrode to which the reference voltage is applied, a gate electrode to which the second gate signal is applied, and a second electrode connected to the sixth node,
the third switch element includes a first electrode connected to the sixth node, a gate electrode to which the second gate signal is applied, and a second electrode connected to the fourth node, and
the fourth switch element includes a first electrode connected to the sixth node, a gate electrode to which the third gate signal is applied, and a second electrode connected to the second node.
5 . The pixel circuit of claim 2 , further comprising:
a fifth switch element configured to apply an anode reset voltage to the fifth node in response to the third gate signal;
a sixth switch element configured to apply a pixel driving voltage to the first node in response to a fourth gate signal; and
a seventh switch element configured to electrically connect the third node to the fifth node in response to a fifth gate signal.
6 . The pixel circuit of claim 5 , wherein
a driving period of the pixel circuit includes a first period, a second period, a third period, a fourth period, and a fifth period,
a voltage of the fourth gate signal is a gate-on voltage during the second and fifth periods and a gate-off voltage during the first, third, and fourth periods,
a voltage of the fifth gate signal is the gate-on voltage during the first, fourth, and fifth periods and the gate-off voltage during the second and third periods, and
each of the first switch element, the second switch element, the third switch element, the fourth switch element, the fifth switch element, the sixth switch element, and the seventh switch element is turned on in response to the gate-on voltage and is turned off in response to the gate-off voltage.
7 . The pixel circuit of claim 5 , wherein
the fifth switch element includes a first electrode connected to the fifth node, a gate electrode to which the third gate signal is applied, and a second electrode to which the anode reset voltage is applied,
the sixth switch element includes a first electrode to which the pixel driving voltage is applied, a gate electrode to which the fourth gate signal is applied, and a second electrode connected to the first node, and
the seventh switch element includes a first electrode connected to the third node, a gate electrode to which the fifth gate signal is applied, and a second electrode connected to the fifth node.
8 . The pixel circuit of claim 1 , wherein the switch circuit includes:
a second switch element configured to apply the reference voltage to a sixth node in response to a second gate signal;
a third switch element configured to apply the reference voltage to the fourth node in response to the second gate signal; and
a fourth switch element configured to electrically connect the sixth node to the second node in response to the third gate signal.
9 . The pixel circuit of claim 8 , wherein
a driving period of the pixel circuit includes a first period, a second period, a third period, a fourth period, and a fifth period,
a voltage of the first gate signal is a gate-on voltage during the third period and a gate-off voltage during the first, second, fourth, and fifth periods,
a voltage of the second gate signal is the gate-on voltage during the first, second, and third periods and the gate-off voltage during the fourth and fifth periods,
a voltage of the third gate signal is the gate-on voltage during the first, second, and fourth periods and the gate-off voltage during the third and fifth periods, and
each of the first switch element, the second switch element, the third switch element, and the fourth switch element is turned on in response to the gate-on voltage and is turned off in response to the gate-off voltage.
10 . The pixel circuit of claim 8 , wherein
the first switch element includes a first electrode connected to a data line to which the data voltage is applied, a gate electrode to which the first gate signal is applied, and a second electrode connected to the second node,
the second switch element includes a first electrode to which the reference voltage is applied, a gate electrode to which the second gate signal is applied, and a second electrode connected to the sixth node,
the third switch element includes a first electrode to which the reference voltage is applied, a gate electrode to which the second gate signal is applied, and a second electrode connected to the fourth node, and
the fourth switch element includes a first electrode connected to the sixth node, a gate electrode to which the third gate signal is applied, and a second electrode connected to the second node.
11 . The pixel circuit of claim 8 , further comprising:
a fifth switch element configured to apply an anode reset voltage to the fifth node in response to the third gate signal;
a sixth switch element configured to apply a pixel driving voltage to the first node in response to a fourth gate signal; and
a seventh switch element configured to electrically connect the third node to the fifth node in response to a fifth gate signal.
12 . The pixel circuit of claim 11 , wherein
a driving period of the pixel circuit includes a first period, a second period, a third period, a fourth period, and a fifth period,
a voltage of the fourth gate signal is a gate-on voltage during the second and fifth periods and a gate-off voltage during the first, third, and fourth periods,
a voltage of the fifth gate signal is the gate-on voltage during the first, fourth, and fifth periods and the gate-off voltage during the second and third periods, and
each of the first switch element, the second switch element, the third switch element, the fourth switch element, the fifth switch element, the sixth switch element, and the seventh switch element is turned on in response to the gate-on voltage and is turned off in response to the gate-off voltage.
13 . The pixel circuit of claim 11 , wherein
the fifth switch element includes a first electrode connected to the fifth node, a gate electrode to which the third gate signal is applied, and a second electrode to which the anode reset voltage is applied,
the sixth switch element includes a first electrode to which the pixel driving voltage is applied, a gate electrode to which the fourth gate signal is applied, and a second electrode connected to the first node, and
the seventh switch element includes a first electrode connected to the third node, a gate electrode to which the fifth gate signal is applied, and a second electrode connected to the fifth node.
14 . The pixel circuit of claim 1 , wherein the switch circuit includes:
a second switch element configured to apply the reference voltage to a sixth node in response to a third gate signal;
a third switch element configured to apply the reference voltage to the fourth node in response to a second gate signal; and
a fourth switch element configured to electrically connect the sixth node to the second node in response to the second gate signal.
15 . The pixel circuit of claim 14 , wherein
a driving period of the pixel circuit includes a first period, a second period, a third period, a fourth period, and a fifth period,
a voltage of the first gate signal is a gate-on voltage during the third period and a gate-off voltage during the first, second, fourth, and fifth periods,
a voltage of the second gate signal is the gate-on voltage during the first, second, and third periods and the gate-off voltage during the fourth and fifth periods,
a voltage of the third gate signal is the gate-on voltage during the first, second, and fourth periods and the gate-off voltage during the third and fifth periods, and
each of the first switch element, the second switch element, the third switch element, and the fourth switch element is turned on in response to the gate-on voltage and is turned off in response to the gate-off voltage.
16 . The pixel circuit of claim 14 , wherein
the first switch element includes a first electrode connected to a data line to which the data voltage is applied, a gate electrode to which the first gate signal is applied, and a second electrode connected to the second node,
the second switch element includes a first electrode to which the reference voltage is applied, a gate electrode to which the third gate signal is applied, and a second electrode connected to the sixth node,
the third switch element includes a first electrode to which the reference voltage is applied, a gate electrode to which the second gate signal is applied, and a second electrode connected to the fourth node, and
the fourth switch element includes a first electrode connected to the sixth node, a gate electrode to which the second gate signal is applied, and a second electrode connected to the second node.
17 . The pixel circuit of claim 14 , further comprising:
a fifth switch element configured to apply an anode reset voltage to the fifth node in response to the third gate signal;
a sixth switch element configured to apply a pixel driving voltage to the first node in response to a fourth gate signal; and
a seventh switch element configured to electrically connect the third node to the fifth node in response to a fifth gate signal.
18 . The pixel circuit of claim 17 , wherein
a driving period of the pixel circuit includes a first period, a second period, a third period, a fourth period, and a fifth period,
a voltage of the fourth gate signal is a gate-on voltage during the second and fifth periods and a gate-off voltage during the first, third, and fourth periods,
a voltage of the fifth gate signal is the gate-on voltage during the first, fourth, and fifth periods and the gate-off voltage during the second and third periods, and
each of the first switch element, the second switch element, the third switch element, the fourth switch element, the fifth switch element, the sixth switch element, and the seventh switch element is turned on in response to the gate-on voltage and is turned off in response to the gate-off voltage.
19 . The pixel circuit of claim 17 , wherein
the fifth switch element includes a first electrode connected to the fifth node, a gate electrode to which the third gate signal is applied, and a second electrode to which the anode reset voltage is applied,
the sixth switch element includes a first electrode to which the pixel driving voltage is applied, a gate electrode to which the fourth gate signal is applied, and a second electrode connected to the first node, and
the seventh switch element includes a first electrode connected to the third node, a gate electrode to which the fifth gate signal is applied, and a second electrode connected to the fifth node.
20 . The pixel circuit of claim 1 , wherein the switch circuit includes:
a second switch element configured to apply the reference voltage to the second node in response to a second gate signal;
a third switch element configured to apply the reference voltage to the fourth node in response to a first gate signal; and
a fourth switch element configured to electrically connect the second node to the fourth node in response to the second gate signal,
wherein the first switch element is turned on or off in response to the first gate signal.
21 . The pixel circuit of claim 20 ,
wherein a driving period of the pixel circuit includes a first period, a second period, a third period, a fourth period, and a fifth period,
a voltage of the first gate signal is a gate-on voltage during the third period and a gate-off voltage during the first, second, fourth, and fifth periods,
a voltage of the second gate signal is the gate-on voltage during the first and second periods and the gate-off voltage during the third, fourth, and fifth periods,
a voltage of a third gate signal is the gate-on voltage during the first, second, third, and fourth periods and the gate-off voltage during the fifth period, and
each of the first switch element, the second switch element, the third switch element, and the fourth switch element is turned on in response to the gate-on voltage and is turned off in response to the gate-off voltage.
22 . The pixel circuit of claim 20 , wherein
the first switch element includes a first electrode connected to a data line to which the data voltage is applied, a gate electrode to which the first gate signal is applied, and a second electrode connected to the second node,
the second switch element includes a first electrode to which the reference voltage is applied, a gate electrode to which the second gate signal is applied, and a second electrode connected to the second node,
the third switch element includes a first electrode to which the reference voltage is applied, a gate electrode to which the first gate signal is applied, and a second electrode connected to the fourth node, and
the fourth switch element includes a first electrode connected to the second node, a gate electrode to which the second gate signal is applied, and a second electrode connected to the fourth node.
23 . The pixel circuit of claim 20 , further comprising:
a fifth switch element configured to apply an anode reset voltage to the fifth node in response to a third gate signal;
a sixth switch element configured to apply a pixel driving voltage to a first sixth-node in response to a fourth gate signal; and
a seventh switch element configured to electrically connect the third node to the fifth node in response to a fifth gate signal.
24 . The pixel circuit of claim 23 , wherein
a driving period of the pixel circuit includes a first period, a second period, a third period, a fourth period, and a fifth period,
a voltage of the fourth gate signal is a gate-on voltage during the second and fifth periods and a gate-off voltage during the first, third, and fourth periods,
a voltage of the fifth gate signal is the gate-on voltage during the first, fourth, and fifth periods and the gate-off voltage during the second and third periods, and
each of the first switch element, the second switch element, the third switch element, the fourth switch element, the fifth switch element, the sixth switch element, and the seventh switch element is turned on in response to the gate-on voltage and is turned off in response to the gate-off voltage.
25 . The pixel circuit of claim 24 , wherein
the fifth switch element includes a first electrode connected to the fifth node, a gate electrode to which the third gate signal is applied, and a second electrode to which the anode reset voltage is applied,
the sixth switch element includes a first electrode to which the pixel driving voltage is applied, a gate electrode to which the fourth gate signal is applied, and a second electrode connected to the first node, and
the seventh switch element includes a first electrode connected to the third node, a gate electrode to which the fifth gate signal is applied, and a second electrode connected to the fifth node.
26 . The pixel circuit of claim 1 , wherein the at least two transistors connected in series include:
a second switch element that includes a gate electrode, a second electrode, and a third electrode; and
a third switch element that includes a gate electrode, a second electrode, and a third electrode, the third electrode of the second switch element being directly connected to the second electrode of the third switch element at a connection node different from the second node and the fourth node.
27 . The pixel circuit of claim 1 , wherein
the first switch element is turned on or off in response to the first gate signal, and
each switch element of the switch circuit is turned on or off in response to signals other than the first gate signal.
28 . A display device comprising:
a display panel including data lines, gate lines, power lines, and pixel circuits;
a data driver configured to output a data voltage of pixel data to the data lines; and
a gate driver configured to sequentially supply a gate signal to the gate lines,
wherein the pixel circuit includes:
a driving element including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node;
a first capacitor connected between the second node and a fourth node;
a second capacitor connected between the third node and the fourth node;
a light-emitting element including an anode electrode connected to a fifth node and a cathode electrode to which a cathode voltage is applied, the light-emitting element configured to be driven by a current supplied through the driving element;
a first switch element configured to connect a data voltage to the second node in response to a first gate signal; and
a switch circuit configured to selectively apply a reference voltage to the second node and the fourth node, the switch circuit including at least two transistors connected in series between the reference voltage and one of the second node and the fourth node.