Techniques for power management control
Described are circuits and techniques to communicate a digital envelope signal from a baseband chipset to a discrete supply modulator power management circuit (PMC).
1 . A system comprising:
a chipset configured to provide one or more RF signals to one or more RF power amplifiers (PAS);
one or more control signal paths coupled to the chipset, wherein the chipset is configured to transmit digitally controlled level (DCL) signals over the one or more control signal paths;
one or more additional signal paths coupled to the chipset, wherein the chipset is configured to transmit one or more additional signals over the one or more additional signal paths; and
a power management circuit (PMC) coupled to the one or more control signal paths and the one or more additional signal paths, the PMC configured to provide one or more supply voltages to the one or more RF PAs based at least in part on the DCL signals and the one or more additional signals.
2 . The system of claim 1 , wherein
the PMC comprises one or more finite state machines (FSMs),
a state of the one or more FSMs corresponding to a voltage level is selected based on both the DCL signals and the one or more additional signals, and
the voltage level is provided as at least one of the one or more supply voltages based on the selected state.
3 . The system of claim 2 , wherein the one or more FSMs are initialized based on the one or more additional signals.
4 . The system of claim 2 , wherein a state of the one or more FSMs represents an operating mode of the PMC.
5 . The system of claim 2 , wherein a state of the one or more FSMs represents a discrete voltage level to be supplied to one or more power amplifiers.
6 . The system of claim 1 , wherein the PMC is configured to change a mapping between a DCL state and a state of the one or more FSMs in response to the one or more additional signals.
7 . The system of claim 2 , wherein the PMC is configured to move the one or more FSMs between adjacent or non-adjacent states, the configuration responsive to the one or more additional signals.
8 . The system of claim 1 , wherein the PMC is configured to change a sequence of states in the one or more FSMs in response to the one or more additional signals.
9 . The system of claim 1 , wherein a specific combination of values communicated by the DCL signals corresponds to an unambiguous state of the one or more FSMs, such that the one or more FSMs in the PMC are moved to the unambiguous state regardless of a prior state of the one or more FSMs.
10 . The system of claim 1 , wherein the one or more additional signal paths comprises a sideline communication signal path comprising a communication bus for conveying information by register write operations.
11 . The system of claim 1 , wherein the one or more additional signal paths comprise one or more auxiliary signal paths.
12 . The system of claim 1 , wherein
the chipset comprises a linear feedback shift register (LFSR) encoder configured to encode the DCL signals prior to transmission over the one or more control signal paths;
the PMC comprises an LFSR decoder configured to decode the encoded DCL signals; and
the one or more additional signals comprise tap and/or seed information for the LFSR decoder.
13 . The system of claim 1 ,
wherein
the one or more control signal paths comprise two one-bit signal lines and do not include any clock lines, and
the chipset is configured to transmit the DCL signals to the PMC over the one or more control signal paths without transmission of an associated clock signal.
14 . The system of claim 13 , wherein the chipset implements multiple electrical connections using single-ended driver circuits.
15 . The system of claim 13 , wherein the chipset comprises an encoder configured to encode finite state machine (FSM) state information as encoded DCL signals for transmission to the PMC via the one or more control signal paths.
16 . The system of claim 15 , further comprising a linear feedback shift register (LFSR) encoder configured to further encode the encoded DCL signals prior to transmission over the one or more control signal paths.
17 . The system of claim 13 , wherein the PMC comprises a finite state machine (FSM) that receives FSM state information transmitted from the chipset.
18 . The system of claim 1 ,
wherein the PMC comprises
input circuitry for receiving the one or more DCL signals, and
one or more supply modulators responsive to the one or more DCL signals.
19 . The system of claim 18 , wherein the PMC further comprises one or more finite state machines (FSMs) controlled at least in part by the one or more additional signal paths.
20 . The system of claim 19 , wherein a mapping between a DCL state and a state of the one or more FSMs is responsive to the one or more additional signals.
21 . The system of claim 19 , wherein:
the one or more supply modulators are responsive to the one or more DCL signals in accordance with a mapping; and
the PMC is capable of reconfiguring the mapping based on the one or more additional signals, such that one or more different supply modulators are responsive to the one or more DCL signals, or such that the one or more supply modulators are responsive to one or more different DCL signals.
22 . The system of claim 19 , wherein the input circuitry of the PMC comprises one or more Schmitt triggers, wherein an output of the one or more Schmitt triggers is provided to the one or more FSMs of the PMC.