IP Library Patent Application 18784218
Patent Application
App. No. 18/784,218

THREE-DIMENSIONAL MEMORY DEVICE WITH THROUGH-STACK CONTACT ASSEMBLIES AND METHODS FOR FORMING THE SAME

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Quick Facts
Patent No.
US None
App. No.
18/784,218
Abstract

A device structure includes an alternating stack of insulating layers and electrically conductive layers. The alternating stack includes a staircase region. A retro-stepped dielectric material portion overlies the alternating stack in the staircase region. A contact assembly includes a layer contact via structure and a finned support assembly. The layer contact via structure vertically extends through the retro-stepped dielectric material portion and includes a contoured bottom surface that includes an annular surface segment that contacts an annular top surface segment of a first electrically conductive layer of the electrically conductive layers. The finned support assembly contacts central surface segments of the contoured bottom surface of the layer contact via structure.

Claims (44)

1 . A device structure, comprising:

an alternating stack of insulating layers and electrically conductive layers, wherein the alternating stack comprises a staircase region;

a retro-stepped dielectric material portion overlying the alternating stack in the staircase region; and

a contact assembly comprising a layer contact via structure, a finned support assembly, and a doped silicate glass portion interposed between the finned support assembly and the layer contact via structure, wherein:

the layer contact via structure vertically extends through the retro-stepped dielectric material portion and comprises a contoured bottom surface that includes an annular surface segment that contacts an annular top surface segment of a first electrically conductive layer of the electrically conductive layers, and the finned support assembly contacts central surface segments of the contoured bottom surface of the layer contact via structure.

2 . The device structure of claim 1 , wherein the doped silicate glass portion comprises at least one dopant species selected from carbon and nitrogen.

3 . The device structure of claim 1 , wherein the doped silicate glass portion comprises a carbon-doped silicate glass containing carbon at an atomic percentage in a range from 1% to 25%.

4 . The device structure of claim 1 , wherein the doped silicate glass portion comprises a nitrogen-doped silicate glass containing nitrogen at an atomic percentage in a range from 1% to 25%.

5 . The device structure of claim 1 , wherein a maximum horizontal cross-sectional area of the doped silicate glass portion is greater than an area of a topmost surface of the finned support assembly.

6 . The device structure of claim 1 , wherein all surface segments of the doped silicate glass portion that overlie a topmost surface of the finned support assembly are in contact with surface segments of the layer contact via structure.

7 . The device structure of claim 1 , wherein the layer contact via structure comprises tubular portion having an outer cylindrical surface that contacts a cylindrical surface segment of an opening through the first electrically conductive layer, and wherein the tubular portion of the layer contact via structure contacts a cylindrical surface segment of the finned support assembly.

8 . The device structure of claim 1 , further comprising a memory opening fill structure vertically extending through the alternating stack, wherein the memory opening fill structure comprises a vertical semiconductor channel and a memory film.

9 . The device structure of claim 1 , wherein the finned support assembly comprises:

a dielectric material portion having a planar top surface that contacts a central bottom surface segment of the doped silicate glass portion; and

a spacer liner that laterally surrounds the dielectric material portion and contacting an annular bottom surface segment of the doped silicate glass portion.

10 . The device structure of claim 9 , wherein the spacer liner comprises an outer cylindrical surface segment that contacts a cylindrical surface segment of the layer contact via structure.

11 . The device structure of claim 9 , wherein:

the dielectric material portion comprises a cylindrical dielectric pillar; and

the finned support assembly further comprises a finned dielectric pillar that laterally surrounds the spacer liner and includes a tubular dielectric portion in contact with the spacer liner and a plurality of dielectric fins that laterally protrude from the tubular dielectric portion.

12 . The device structure of claim 11 , wherein the plurality of dielectric fins are located at levels of a subset of the insulating layers that underlie the first electrically conductive layer.

13 . The device structure of claim 11 , wherein the spacer liner comprises a semiconductor material or silicon oxycarbide.

14 . The device structure of claim 9 , wherein

the dielectric material portion comprises finned dielectric pillar that includes a cylindrical dielectric portion and a plurality of dielectric fins that laterally protrude from the cylindrical dielectric portion; and

the spacer liner comprises a plurality of laterally-protruding portions that embed the plurality of dielectric fins.

15 . The device structure of claim 9 , further comprising a layer stack including a silicon oxide buffer layer and a silicon nitride buffer layer and interposed between the alternating stack and the retro-stepped dielectric material portion in the staircase region, wherein:

the layer contact via structure vertically extends through the layer stack; and

the layer contact via structure comprises an annular convex sidewall surface that contacts an annular concave sidewall surface of the silicon nitride buffer layer.

16 . A method of forming a device structure, comprising:

forming an alternating stack of insulating layers and sacrificial material layers over a substrate;

forming stepped surfaces by patterning the alternating stack;

forming a retro-stepped dielectric material portion overlying the stepped surfaces;

forming a contact via cavity through the retro-stepped dielectric material portion and the alternating stack;

forming a combination of a finned support assembly, a doped silicate glass portion overlying the finned support assembly, and a sacrificial contact via structure in the contact via cavity;

replacing the sacrificial material layers with electrically conductive layers; and

replacing the sacrificial contact via structure with a layer contact via structure that directly contacts an annular surface segment of a first electrically conductive layer of the electrically conductive layers.

17 . The method of claim 16 , further comprising laterally recessing surface portions of the insulating layers and the retro-stepped dielectric material portion around the contact via cavity by performing a selective isotropic etch process, wherein annular fin cavities are formed in volumes from which portions of the insulating layers are removed, and an upper portion of the contact via cavity is laterally expanded at a level of the retro-stepped dielectric material portion.

18 . The method of claim 17 , further comprising:

depositing at least one fill material that includes a silicate glass material in the contact via cavity, wherein portions of the contact via cavity laterally surrounded by the alternating stack are filled with the at least one fill material, and wherein a cylindrical cavity is present within the upper portion of the contact via cavity; and

implanting at least one dopant species selected from nitrogen and carbon into a portion of the silicate glass material that underlies the cylindrical cavity and overlies the alternating stack to form the doped silicate glass portion.

19 . The method of claim 18 , further comprising removing an unimplanted portion of the silicate glass material selective to the doped silicate glass portion.

20 . The method of claim 18 , further comprising:

forming a layer stack including a silicon oxide buffer layer and a silicon nitride buffer layer over the stepped surfaces, wherein the retro-stepped dielectric material portion is formed over the layer stack, and wherein the contact via cavity is formed through the layer stack;

performing an etch processes that etches the layer stack selective to the doped silicate glass portion; and

performing at least one additional etch process that physically exposes an annular top surface segment of one of the sacrificial material layers.

Assignments (4)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2024
From: TAKAHASHI, AKIRA; MATSUNO, KOICHI
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 068892/0886 →