IP Library › Granted Patent US 12,635,239
Granted Patent B2
US 12,635,239 · App. 18/798,914 · Granted May 19, 2026

Display device and semiconductor device

Inventors: Toshihide Jinnai (Tokyo, JP); Hajime Watakabe (Tokyo, JP); Akihiro Hanada (Tokyo, JP); Ryo Onodera (Tokyo, JP); Isao Suzumura (Tokyo, JP)
Assignee: MAGNOLIA WHITE CORPORATION
H10D86/423G02F1/136227G02F1/136286G02F1/1368H10D30/6745H10D86/441H10D86/60H10K59/131H10K59/80515H10K59/80521G02F2201/123
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,635,239
App. No.
18/798,914
Granted
May 19, 2026
Kind
B2
Abstract

A display device including a substrate having a first TFT of an oxide semiconductor and a second TFT of a polysilicon semiconductor comprising: the oxide semiconductor is covered by a first insulating film, a first drain electrode is connected to the oxide semiconductor via a first through hole formed in the first insulating film, a first source electrode is connected to the oxide semiconductor via second through hole formed in the first insulating film in the first TFT, a second insulating film is formed covering the first drain electrode and the first source electrode, a drain wiring connects to the first drain electrode via a third through hole formed in the second insulating film, a source wiring is connected to the first source electrode via a fourth through hole formed in the second insulating film.

Claims (24)

1 . A semiconductor device including a substrate having a first thin film transistor and a second thin film transistor, wherein

the first thin film transistor has a first semiconductor layer which is oxide semiconductor, a first gate electrode layer, a first gate insulating film arranged between the first semiconductor layer and the first gate electrode layer, a first drain electrode layer and a first source electrode layer,

a passivation film is formed covering the first gate electrode layer,

the second thin film transistor has a second semiconductor layer which is a polysilicon semiconductor, a second gate electrode layer, a second gate insulating film arranged between the second semiconductor layer and the second gate electrode layer, a second drain electrode layer and a second source electrode layer,

an interlayer insulating film is arranged between the first semiconductor layer and the second semiconductor layer,

the first semiconductor layer is disposed in an upper layer than the second semiconductor layer,

the first drain electrode layer is connected to the first semiconductor layer via a first through hole formed in the first gate insulating film,

the first source electrode layer is connected to the first semiconductor layer via a second through hole formed in the first gate insulating film,

a gate wiring is extended in a first direction, a signal wiring is extend in a second direction crossing the first direction,

the first semiconductor layer is arranged to intersect the gate wiring, in a plan view,

the signal wiring is formed on the passivation film and connects to the first drain electrode layer via a third through hole formed in the passivation film,

a first metal film is arranged below the first semiconductor layer and overlaps the first semiconductor layer in plan view,

a second metal film is arranged below the second semiconductor layer and overlaps the second semiconductor layer in plan view.

2 . The semiconductor device according to claim 1 , wherein

an aluminum oxide film is arranged between the first gate insulating film and the first gate electrode layer.

3 . The semiconductor device according to claim 1 , wherein

the second drain electrode and the second source electrode are formed on the passivation film,

a fifth through hole is formed through the first gate insulating film, the interlayer insulating film, the second gate insulating film and the passivation film, the second drain electrode is connected to the second semiconductor layer via a fifth through hole,

a sixth through hole is formed through the first gate insulating film, the interlayer insulating film, the second gate insulating film and the passivation film, the second source electrode is connected to the second semiconductor layer via a sixth through hole.

4 . The semiconductor device according to claim 1 , wherein

the first through hole and the third through hole are set in different places and overlap the drain wiring in a plan view.

5 . The semiconductor device according to claim 1 , wherein

a source wiring connects to the first source electrode via a fourth through hole formed in the passivation film, and

the source wiring connects with a pixel electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 071619/0050 →
Priority Claims (1)
JP 2019-027237 · Feb 19, 2019 · national
Continuity (4)
Continuation 17987887 · Nov 16, 2022
Continuation 17506694 · Oct 21, 2021
Continuation 16787054 · Feb 11, 2020
Related Publication 20240402552A1 · Dec 5, 2024
References Cited (5)
US 11550195B2 · Jinnai · 2023 [cited by examiner]
US 12085823B2 · Jinnai · 2024 [cited by examiner]
US 20020139983A1 · Choi · 2002 [cited by examiner]
US 20040209005A1 · Goto · 2004 [cited by examiner]
US 20170299929A1 · Ochiai · 2017 [cited by examiner]