IP Library › Granted Patent US 11,550,195
Granted Patent B2
US 11,550,195 · App. 17/506,694 · Granted Jan 10, 2023

Display device and semiconductor device

Inventors: Toshihide Jinnai (Tokyo, JP); Hajime Watakabe (Tokyo, JP); Akihiro Hanada (Tokyo, JP); Ryo Onodera (Tokyo, JP); Isao Suzumura (Tokyo, JP)
Assignee: JAPAN DISPLAY INC.
G02F1/136286G02F1/1368G02F1/136227H01L27/124H01L27/3276H01L29/78672G02F2201/123
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Quick Facts
Patent No.
US 11,550,195
App. No.
17/506,694
Granted
Jan 10, 2023
Kind
B2
Abstract

A display device including a substrate having a first TFT of an oxide semiconductor and a second TFT of a polysilicon semiconductor comprising: the oxide semiconductor 109 is covered by a first insulating film, a first drain electrode 110 is connected to the oxide semiconductor 109 via a first through hole 132 formed in the first insulating film, a first source electrode 111 is connected to the oxide semiconductor 109 via second through hole 133 formed in the first insulating film in the first TFT, a second insulating film is formed covering the first drain electrode 110 and the first source electrode 111, a drain wiring connects 12 to the first drain electrode 110 via a third through hole 130 formed in the second insulating film, a source wiring 122 is connected to the first source electrode 111 via a fourth through hole 131 formed in the second insulating film.

Claims (25)

1. A semiconductor device including a substrate having a first TFT (thin film transistor) and a second TFT, wherein

the first TFT has a first semiconductor layer, a first gate insulating film covering the first semiconductor layer and a first gate electrode on the first gate insulating film,

a passivation film is formed covering the first gate electrode,

the second TFT has a second semiconductor layer, a second gate insulating film covering the second semiconductor layer and a second gate electrode on the second gate insulating film,

the first semiconductor layer is an oxide semiconductor layer,

an interlayer insulating film is arranged between the first TFT and the second TFT,

the second TFT is set nearer to the substrate than the first TFT,

a first drain electrode is connected to the first semiconductor layer via a first through hole formed in the first gate insulating film,

a first source electrode is connected to the first semiconductor layer via a second through hole formed in the first gate insulating film,

a plurality of scanning wirings extend in a first direction and are arranged in the second direction, a plurality of drain wirings extend in the second direction and are arranged in the first direction,

the first semiconductor layer has a bent portion and is arranged to intersect the scanning wiring, in a plan view,

the drain wiring and a source wiring are formed on the passivation film, and

the drain wiring connects to the first drain electrode via a third through hole formed in the passivation film, the source wiring connects to the first source electrode via a fourth through hole formed in the passivation film.

2. The semiconductor device according to claim 1 ,

wherein the second semiconductor layer is a polysilicon semiconductor layer.

3. The semiconductor device according to claim 1 ,

a second drain electrode and a second source electrode are formed on the passivation film,

a fifth through hole is formed through the first gate insulating film, the interlayer insulating film, the second gate insulating film and the passivation film, the second drain electrode is connected to the second semiconductor layer via a fifth through hole,

a sixth through hole is formed through the first gate insulating film, the interlayer insulating film, the second gate insulating film and the passivation film, the second source electrode is connected to the second semiconductor layer via a sixth through hole.

4. The semiconductor device according to claim 1 ,

wherein the first through hole and the third through hole are set in different places and overlap the drain wiring in a plan view.

5. The semiconductor device according to claim 1 ,

wherein the drain wiring is a video signal wiring.

6. The semiconductor device according to claim 5 ,

wherein the source wiring connects with a pixel electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072130/0313 →
Priority Claims (1)
JP JP2019-027237 · Feb 19, 2019 · national
Continuity (2)
Continuation 16787054 · Feb 11, 2020
Related Publication 20220043316A1 · Feb 10, 2022
Cited By (1)
US 12,635,239