Clock generator and method of clock generation

1 . A clock generator comprising:

a ring oscillator configured to generate an output frequency signal;

a frequency detector configured to compare a frequency of the output frequency signal with r times a frequency of a reference frequency signal and to generate a feedback signal based on the comparison; and

a control circuit configured to control a loop delay parameter of the ring oscillator and a supply voltage of the ring oscillator based on the feedback signal, wherein the control circuit is configured:

to reduce the frequency of the output frequency signal when its frequency is higher than r times the frequency of the reference frequency signal by reducing the supply voltage without modifying the loop delay parameter, unless the supply voltage has reached a minimal level, in which case the loop delay parameter is then increased; and

to increase the frequency of the output frequency signal when its frequency is lower than r times the frequency of the reference frequency signal by reducing the loop delay parameter without modifying the supply voltage, unless the loop delay parameter has reached a minimal level, in which case the supply voltage is then increased.

2 . The clock generator of claim 1 , wherein the control circuit is configured to prevent modifications of the supply voltage once the control circuit has detected that the loop delay parameter has reached its minimal level.

3 . The clock generator of claim 1 , wherein the control circuit is configured to iteratively reduce and/or increase the loop delay parameter, the reduction or increase upon each iteration being equal to a step size.

4 . The clock generator of claim 3 , wherein the step size is variable as a function of a frequency difference between the frequency of the output frequency signal and the frequency of the reference frequency signal.

5 . The clock generator of claim 3 , wherein the step size is equal to a first size until the loop delay parameter reaches the minimal level, and to a second size, lower than the first size, after the loop delay parameter has reached the minimal level.

6 . The clock generator of claim 1 , further comprising a sigma-delta converter configured to convert the loop delay parameter into a plurality of control signals configured to control the ring oscillator.

7 . The clock generator of claim 1 , wherein the frequency detector is configured to compare the frequency of the output frequency signal with r times the frequency of the reference frequency signal by comparing the output frequency signal with r times the frequency of the reference frequency signal.

8 . The clock generator of claim 1 , wherein the ring oscillator comprises a plurality of delay stages coupled in series, each delay stage being configured to be activated or deactivated by the loop delay parameter.

9 . The clock generator of claim 8 , wherein each delay stage comprising:

a multiplexer;

a delay element coupled to a first input of the multiplexer, the first input being selected by a first state of a control signal of the multiplexer;

a bypass path coupled to a second input of the multiplexer, the second input being selected by a second state of the control signal of the multiplexer; and

a logic gate coupling the output of a previous stage to an input of the delay element, the logic gate receiving the control signal of the multiplexer and being configured to supply a constant signal to the delay element while the control signal is in the second state.

10 . The clock generator of claim 1 , wherein r is a real number greater than 1.

11 . An integrated circuit comprising:

an electronic circuit controlled by a clock signal; and

the clock generator of claim 1 configured to supply the clock signal to the electronic circuit.

12 . The integrated circuit of claim 11 , further comprising:

a voltage regulator configured to generate said supply voltage; and

a further electronic circuit powered by said supply voltage.

13 . A method of clock generation comprising:

generating, by a ring oscillator, an output frequency signal;

comparing, by a frequency detector, a frequency of the output frequency signal with r times a frequency of a reference frequency signal in order to generate a feedback signal based on the comparison; and

controlling, by a control circuit based on the feedback signal, a loop delay parameter of the ring oscillator and a supply voltage of the ring oscillator, by:

reducing the frequency of the output frequency signal when its frequency is higher than r times the frequency of the reference frequency signal by reducing the supply voltage without modifying the loop delay parameter, unless the supply voltage has reached a minimal level, in which case the loop delay parameter is then increased; and increasing the frequency of the output frequency signal when its frequency is lower than r times the frequency of the reference frequency signal by reducing the loop delay parameter without modifying the supply voltage, unless the loop delay parameter has reached a minimal level, in which case the supply voltage is then increased.

14 . The method of claim 13 , wherein the ring oscillator comprises a plurality of delay stages coupled in series, and wherein reducing the loop delay parameter causes the deactivation of one or more of said delay stages.