SEMICONDUCTOR PACKAGING STRUCTURE, SEMICONDUCTOR COMPONENT AND ELECTRONIC DEVICE
A semiconductor packaging structure includes: a first packaging body and a second packaging body. The first packaging body includes a first substrate and a first chip located on the first substrate. The second packaging body is coupled onto the first packaging body and includes a second substrate. The first chip is located between the first substrate and the second substrate. A ratio of a thickness T 1 of the first chip to a distance D 1 between the first substrate and the second substrate is less than 0.5.
1 . A semiconductor packaging structure, comprising:
a first packaging body comprising a first substrate and a first chip, said first chip located on the first substrate; and
a second packaging body coupled to the first packaging body, said second packaging body comprising a second substrate, the first chip being located between the first substrate and the second substrate;
wherein a ratio of a thickness of the first chip T 1 to a distance between the first substrate and the second substrate D 1 is less than 0.5.
2 . The semiconductor packaging structure of claim 1 , wherein T 1 is between 50 μm and 90 μm.
3 . The semiconductor packaging structure of claim 1 , further comprising:
a heat dissipation structure disposed on the first chip.
4 . The semiconductor packaging structure of claim 3 , wherein the heat dissipation structure is disposed between the first chip and the second substrate, and wherein the heat dissipation structure is in direct contact with, and covers a first upper surface of the first chip, the first upper surface being a surface of the first chip away from the first substrate.
5 . The semiconductor packaging structure of claim 4 , wherein a ratio of a thickness of the heat dissipation structure T 2 to the distance between the first substrate and the second substrate D 1 is between 0.3 and 0.5.
6 . The semiconductor packaging structure of claim 5 , wherein T 2 is between 5 μm and 40 μm.
7 . The semiconductor packaging structure of claim 4 , wherein a distance between the heat dissipation structure and the second substrate D 2 is not greater than 40 μm.
8 . The semiconductor packaging structure of claim 3 , wherein the heat dissipation structure comprises one of a diamond material, a silicon material or a copper material.
9 . The semiconductor packaging structure of claim 1 , wherein the first packaging body further comprises:
an encapsulation layer filled between the first substrate and the second substrate, and wrapping around and encapsulating the first chip; and
a conductive structure located in the encapsulation layer, disposed at a periphery of the first chip, and electrically connecting the first substrate with the second substrate.
10 . The semiconductor packaging structure of claim 9 , further comprising:
a first wiring layer, disposed in the first substrate, and electrically connected with a first lower surface of the first chip, the first lower surface being a surface of the first chip near the first substrate; and
a second wiring layer, disposed in the second substrate, and electrically connected with the first wiring structure via the conductive structure.
11 . The semiconductor packaging structure of claim 1 , further comprising:
a heat dissipation structure located on a surface of the second substrate away from the first substrate,
wherein a vertical projection of the first chip on the first substrate at least partially overlaps with a vertical projection of the heat dissipation structure on the first substrate in a direction perpendicular to a surface of the first substrate.
12 . The semiconductor packaging structure of claim 1 , further comprising:
a heat dissipation structure penetrating through the second substrate, wherein the heat dissipation structure is in contact with and covering a first upper surface of the first chip,
wherein a vertical projection of the first chip on the first substrate at least partially overlaps with a vertical projection of the heat dissipation structure on the first substrate in a direction perpendicular to a surface of the first substrate.
13 . The semiconductor packaging structure of claim 1 , further comprising:
a heat dissipation structure penetrating through the second substrate, wherein the heat dissipation structure is at a predetermined distance from a first upper surface of the first substrate,
wherein a vertical projection of the first chip on the first substrate at least partially overlaps with a vertical projection of the heat dissipation structure on the first substrate in a direction perpendicular to a surface of the first substrate.
14 . The semiconductor packaging structure of claim 1 , further comprising:
a heat dissipation structure,
wherein the second structure comprises a groove not penetrating through the second substrate, and the heat dissipation structure is filled in the groove,
wherein a vertical projection of the first chip on the first substrate at least partially overlaps with a vertical projection of the heat dissipation structure on the first substrate in a direction perpendicular to a surface of the first substrate.
15 . A semiconductor component, comprising a semiconductor packaging structure comprising:
a first packaging body comprising a first substrate and a first chip located on the first substrate; and
a second packaging body coupled to the first packaging body and comprising a second substrate, the first chip being located between the first substrate and the second substrate;
wherein a ratio of a thickness of the first chip T 1 to a distance between the first substrate and the second substrate D 1 is less than 0.5.
16 . The semiconductor component of claim 15 , wherein T 1 is between 50 μm and 90 μm.
17 . The semiconductor component of claim 1 , wherein semiconductor packaging structure further comprises: a heat dissipation structure disposed on the first chip.
18 . An electronic device, comprising a semiconductor packaging structure, comprising:
a first packaging body comprising a first substrate and a first chip located on the first substrate; and
a second packaging body coupled to the first packaging body and comprising a second substrate, the first chip being located between the first substrate and the second substrate;
wherein a ratio of a thickness of the first chip T 1 to a distance between the first substrate and the second substrate D 1 is less than 0.5.
19 . The electronic device of claim 18 , wherein T 1 is between 50 μm and 90 μm.
20 . The electronic device of claim 18 , wherein semiconductor packaging structure further comprises: a heat dissipation structure disposed on the first chip.