THREE-DIMENSIONAL MEMORY DEVICE WITH LATERALLY INTEGRATED ACCESS TRANSISTORS AND METHOD OF MAKING THE SAME
A device structure includes a three-dimensional array of unit cells containing vertical stacks of the unit cells arranged along a vertical direction. Each of the unit cells includes an access field effect transistor containing a set of semiconductor material portions that includes a horizontally-extending semiconductor channel and a storage device having a first electrode electrically connected to a sidewall of the set of semiconductor material portions, a second electrode that is spaced from the access field effect transistor, and a memory layer located between the first electrode and the second electrode. Alternatively, the storage device may be a memory field effect transistor containing a ferroelectric or charge trapping gate dielectric layer.
1 . A device structure comprising a three-dimensional array of unit cells comprising vertical stacks of the unit cells arranged along a vertical direction, wherein each of the unit cells comprises:
an access field effect transistor comprising a set of semiconductor material portions that includes a horizontally-extending semiconductor channel; and
a storage device having a first electrode electrically connected to a sidewall of the set of semiconductor material portions, a second electrode that is spaced from the access field effect transistor, and a memory layer located between the first electrode and the second electrode.
2 . The device structure of claim 1 , wherein the first electrode physically contacts the sidewall of the set of semiconductor material portions.
3 . The device structure of claim 2 , wherein the first electrode comprises:
an end conductive plate that is perpendicular to the first horizontal direction;
a top conductive plate adjoined to a top of the end conductive plate and laterally extending along the first horizontal direction;
a bottom conductive plate adjoined to a bottom of the end conductive plate and laterally extending along the first horizontal direction;
a first conductive sidewall plate adjoined to a first vertically extending edge of the end conductive plate and laterally extending along the first horizontal direction; and
a second conductive sidewall plate adjoined to a second vertically extending edge of the end conductive plate and laterally extending along the first horizontal direction.
4 . The device structure of claim 3 , wherein:
a top surface of the set of semiconductor material portions and a top surface of the top conductive plate are located in a first horizontal plane;
a bottom surface of the set of semiconductor material portions and a bottom surface of the bottom conductive plate are located in a second horizontal plane;
a first sidewall of the set of semiconductor material portions and an outer sidewall of the first conductive sidewall plate are located in a first vertical plane that is parallel to the first horizontal direction; and
a second sidewall of the set of semiconductor material portions and an outer sidewall of the second conductive sidewall plate are located in a second vertical plane that is parallel to the first horizontal direction.
5 . The device structure of claim 1 , wherein the set of semiconductor material portions further comprises a source region in contact with the first electrode, and drain region located on an opposite side of the horizontally-extending channel relative to the source region.
6 . The device structure of claim 5 , wherein:
the horizontally-extending semiconductor channel and the source region have a same uniform vertical cross-sectional shape within any vertical cross-sectional view that cuts through the horizontally-extending semiconductor channel or the source region, and is perpendicular to the first horizontal direction irrespective of a location of a vertical cut plane for a respective vertical cross-sectional view; and
the drain region has a variable vertical cross-sectional shape within vertical planes that are perpendicular to the first horizontal direction as a function of a lateral distance from the horizontally-extending semiconductor channel.
7 . The device structure of claim 5 , wherein the access field effect transistor further comprises:
a tubular gate dielectric that laterally surrounds the horizontally-extending semiconductor channel and laterally extends along the first horizontal direction; and
a gate electrode that wraps around the tubular gate dielectric in a vertical cross-sectional view that is perpendicular to the first horizontal direction.
8 . The device structure of claim 7 , wherein:
the gate electrode comprises a portion of a word line that laterally extends along a second horizontal direction as a gate electrode; and
the tubular gate dielectric comprises a top dielectric portion contacting a horizontal top surface of the horizontally-extending semiconductor channel, a bottom dielectric portion contacting a horizontal bottom surface of the horizontally-extending semiconductor channel, and a pair of sidewall dielectric portions contacting a pair of sidewalls of the horizontally-extending semiconductor channel; and
each of the top dielectric portion, the bottom dielectric portion, and the pair of sidewall dielectric portions is contacted by the gate electrode.
9 . The device structure of claim 5 , further comprising a vertical bit line contacting the drain regions of a respective one of the vertical stacks, and a vertical write line electrically connected to the second electrodes of the respective one of the vertical stacks.
10 . The device structure of claim 1 , wherein the three-dimensional array of the unit cells further comprises:
rows of respective unit cells arranged along a second horizontal direction that is different from the first horizontal direction; and
columns of respective unit cells arranged along the first horizontal direction.
11 . The device structure of claim 10 , further comprising a two-dimensional array of vertical bit lines and vertical write lines.
12 . The device structure of claim 11 , wherein:
each of the vertical bit lines contacts a set of drain regions located within a respective one of the vertical stacks of unit cells;
each of the vertical write lines comprises a vertical conductive wall structure that laterally extends along the second horizontal direction; and
each of the second electrodes comprises a conductive lateral protrusion that laterally protrudes from the conductive wall structure along the first horizontal direction.
13 . The device structure of claim 1 , wherein the storage device is a ferroelectric capacitor, and memory layer comprises a ferroelectric dielectric material.
14 . The device structure of claim 1 , wherein the storage device is a charge storage capacitor, and memory layer comprises a charge storage dielectric material.
15 . The device structure of claim 1 , wherein the storage device is a variable resistor, and the memory layer comprises a material selected from:
a filament-forming resistive dielectric material;
an oxygen vacancy-modulated resistive dielectric material;
a phase change material; or
a polymer material exhibiting resistive switching properties.
16 . A method of forming a device structure, comprising:
forming a three-dimensional array of horizontally-extending semiconductor rails laterally extending along a first horizontal direction over a substrate, wherein the three-dimensional array of horizontally-extending semiconductor rails is structurally supported by a three-dimensional array of horizontally-extending sacrificial rails;
forming first inter-rail cavities between vertically-neighboring pairs of first portions of the horizontally-extending semiconductor rails by removing a first portion of each of the horizontally-extending sacrificial rails;
depositing a gate dielectric material and a gate electrode material around each first portion of the horizontally-extending semiconductor rails;
forming second inter-rail cavities between the vertically-neighboring pairs of the horizontally-extending semiconductor rails by removing a second portion of each of the horizontally-extending sacrificial rails;
patterning the gate dielectric material and the gate electrode material into a three-dimensional array of gate dielectrics and a two-dimensional array of word lines; and
replacing second portions of the horizontally-extending semiconductor rails with a three-dimensional array of instances of an storage device.
17 . The method of claim 16 , wherein the storage device comprises a two terminal device comprising a first electrode, a second electrode, and a memory layer located between the first electrode and the second electrode.
18 . The method of claim 17 , wherein the storage device comprises a ferroelectric capacitor.
19 . The method of claim 17 , wherein the storage device comprises a charge storage capacitor.
20 . The method of claim 17 , wherein the storage device comprises a variable resistor.