Granted Patent B2

US 12,591,633 · App. 18/830,123 · Granted Mar 31, 2026

Inventor: William Martin Snelgrove (Toronto, CA)

Assignee: UNTETHER AI CORPORATION

G06F17/16G06F7/5324G06F7/5443G06F7/575G06F9/30101

Abstract

Claims (34)

1 . A processing device comprising:

a two-dimensional array of processing elements, each processing element including:

an arithmetic logic unit to perform an operation;

an input selector to select input to the processing element from one of its neighboring processing elements;

an output selector to select output from the processing element to a different one its neighboring processing elements; and

interconnections among the array of processing elements to provide direct communication between each processing element and its neighboring processing elements; and

a controller connected to the array of processing elements, the controller configured to:

load an input vector into the array of processing elements;

divide a non-square matrix of coefficients into a plurality of square submatrices of coefficients;

load each square submatrix of coefficients into the array of processing elements as serialized coefficients;

control the array of processing elements to perform a computation with each loaded square submatrix of coefficients and the input vector by:

performing a parallel operation with the serialized coefficients in the array of processing elements and the input vector;

accumulating a result vector; and

rotating the result vector in the array of processing elements and repeating the performing of the parallel operation and the accumulating until the operation is complete; and

when each of the computations is complete, outputting the result vector.

2 . The processing device of claim 1 wherein the controller is further configured to:

combine the result vector of each of the computations to obtain a final result vector corresponding to the non-square matrix of coefficients.

3 . The processing device of claim 1 wherein the controller is further configured to:

divide the input vector into a plurality of input vector portions, each of the plurality of input vector portions corresponding to one of the plurality of square submatrices of coefficients; and

perform the computation with each loaded square submatrix of coefficients and its corresponding input vector portion.

4 . A system comprising a controller and a two-dimensional array of processing elements, wherein the controller is configured to:

load an input vector into the array of processing elements;

divide a non-square matrix of coefficients into a plurality of square submatrices of coefficients;

load each square submatrix of coefficients into the array of processing elements as serialized coefficients;

control the array of processing elements to perform a computation with each loaded square submatrix of coefficients and the input vector by:

performing a parallel operation with the serialized coefficients in the array of processing elements and the input vector;

accumulating a result vector; and

rotating the result vector in the array of processing elements and repeating the performing of the parallel operation and the accumulating until the operation is complete; and

when each of the computations is complete, outputting the result vector.

5 . The controller of claim 4 further configured to:

combine the result vector of each of the computations to obtain a final result vector corresponding to the non-square matrix of coefficients.

6 . The controller of claim 4 further configured to:

divide the input vector into a plurality of input vector portions, each of the plurality of input vector portions corresponding to one of the plurality of square submatrices of coefficients; and

perform the computation with each loaded square submatrix of coefficients and its corresponding input vector portion.

Assignments (3)

Continuity (8)

References Cited (73)