IP Library › Granted Patent US 12,453,150
Granted Patent B2
US 12,453,150 · App. 18/846,211 · Granted Oct 21, 2025

Manufacturing method for power semiconductor device using low-energy electron radiation to produce silicon-enriched layer

Inventors: Giovanni Alfieri (Möriken, CH); Gianpaolo Romano (Baden, CH)
Assignee: HITACHI ENERGY LTD
H10D62/8325H01L21/0475H10D64/027
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Quick Facts
Patent No.
US 12,453,150
App. No.
18/846,211
Granted
Oct 21, 2025
Kind
B2
Abstract

A method for producing a power semiconductor device comprises providing a semiconductor body based on SiC, irradiating at least a first portion of a top side of the semiconductor body with low-energy electron radiation, and producing an electrical insulation layer at least in the at least one irradiated first portion.

Claims (14)

1. A method for producing a power semiconductor device comprising the following steps:

providing a semiconductor body based on SiC,

irradiating at least one first portion of a top side of the semiconductor body with low-energy electron radiation having a kinetic energy of at least 116 keV and at most 210 keV, by means of the low-energy electron radiation in the at least one first portion carbon atoms are moved from the top side into the semiconductor body so that after irradiating the at least one first portion, there the semiconductor body has a layer of Si 0.5+x C 0.5−x , wherein x is at least 0.001 and is at most 0.1, said layer has a thickness of at least 10 nm and of at most 0.2 μm, and

producing an electrical insulation layer at least in the at least one irradiated first portion, wherein the electrical insulation layer is of SiO 2 .

2. The method according to claim 1 , wherein x is at most 0.02.

3. The method according to claim 1 , wherein a dose of the low-energy electron radiation in the first portion is at least 10 12 cm −2 and at most 10 17 cm −2 .

4. The method according to claim 1 , wherein by producing the electrical insulation layer, an SiO 2 /n-type 4H—SiC interface is produced.

5. The method according to claim 1 , wherein the producing the electrical insulation layer includes annealing a previously applied material of the electrical insulation layer.

6. The method according to claim 5 , wherein the annealing is done in an atmosphere containing at least one of nitrogen and oxygen.

7. The method according to claim 1 , wherein the irradiating the at least one first portion is done in a nitrogen-containing atmosphere.

8. The method according to claim 1 , wherein the top side is a planar surface of the semiconductor body.

9. The method according to claim 1 , further including forming at least one trench into the semiconductor body prior to irradiating the at least one first portion, wherein the at least one first portion includes side walls and a bottom face of the at least one trench.

10. The method according to claim 1 , wherein prior to irradiating the at least one first portion, a mask material is applied on the top side, during irradiating the at least one first portion the at least one first portion is free of the mask material while remaining portions of the top side are covered by the mask material.

11. The method according to claim 1 , wherein directly on a side of the electrical insulation layer remote from the semiconductor body a gate electrode is formed, the gate electrode is of poly-Si, wherein, seen in cross-section perpendicular to the top side, the electrical insulation layer as well as the gate electrode extend as hole-free, closed layers across a well region from a source region to a drain region.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2024
From: ALFIERI, GIOVANNI; ROMANO, GIANPAOLO
To: HITACHI ENERGY SWITZERLAND AG
Reel/Frame 068565/0339 →
MERGER Recorded Sep 12, 2024
From: HITACHI ENERGY SWITZERLAND AG
To: HITACHI ENERGY LTD
Reel/Frame 068566/0293 →
Priority Claims (1)
EP 22162144 · Mar 15, 2022 · regional
Continuity (1)
Related Publication 20250113570A1 · Apr 3, 2025
References Cited (28)
US 20020034852A1 · Alok · 2002 [cited by applicant]
US 20120241767A1 · Yano et al. · 2012 [cited by applicant]
US 20130168698A1 · Lee · 2013 [cited by examiner]
US 20170141206A1 · Koga · 2017 [cited by applicant]
US 20180308937A1 · Hirose et al. · 2018 [cited by applicant]
US 20190296146A1 · Shimizu et al. · 2019 [cited by applicant]
US 20220028976A1 · Wirths · 2022 [cited by examiner]
CN 114005742A · 2022 [cited by applicant]
JP 2011109018A · 2011 [cited by applicant]
JP 2019169487A · 2019 [cited by applicant]
JP 2022508324A · 2022 [cited by applicant]
“Low-temperature chemical-vapor deposition of 3C—SiC films on Si(1 0 0) using SiH4—C2H4—HCl—H2” by Y. Gao, J.H. Edgar, J. Chaudhuri, S.N. Cheema, M.V. Sidorov, D.N. Braski in Journal of Crystal Growth 191 (1998) 439-445… [cited by examiner]
“The effects of displacement threshold irradiation energy on deep levels in p-type 6H—SiC” by G Alfieri and T Kimoto in J. Phys.: Condens. Matter 23 (2011) 065803 (Year: 2011). [cited by examiner]
“Deep levels created by low energy electron irradiation in 4H—SiC” by L. Storasta, J. P. Bergman, E. Janzen, and A. Henry, in J. Appl. Phys. 96, 4909-4915 (2004) (Year: 2004). [cited by examiner]
Aaron Modic et al., “High Channel Mobility 4H—SiC MOSFETs by Antimony Counter-Doping”, IEEE Electron Device Letters, vol. 35, No. 9, Sep. 2014, 3 pages. [cited by applicant]
D. Dutta et al., “Evidence for carbon clusters present near thermal gate oxides affecting the electronic band structure in SiC-MOSFET”, Applied Physics Letters, 101601, Sep. 6, 2019, 5 pages. [cited by applicant]
Fabien Devynck, “Defect levels of carbon-related defects at the SiC/SiO2 interface from hybrid functionals”; Physical Review B 83, 195319, 2011, 11 pages. [cited by applicant]
Francesco Moscatelli et al., “Nitrogen Implantation to Improve Electron Channel Mobility in 4H—SiC MOSFET”, IEEE Transactions on Electron Devices, vol. 55, No. 4, Apr. 2008, 7 pages. [cited by applicant]
Gang Liu et al., “Enhanced Inversion Mobility on 4H—SiC (1120) Using Phosphorus and Nitrogen Interface Passivation”, IEEE Electron Device Letters, vol. 34, No. 2, 2013, 4 pages. [cited by applicant]
K. Danno et al., “Investigation of carrier lifetime in 4H—SiC epilayers and lifetime control by electron irradiation”, Applied Physics Letters 90, 202109, 2007, 4 pages. [cited by applicant]
Koutarou Kawahara et al., “Reduction of deep levels generated by ion implantation into n- and p-type 4H—SiC”, Journal of Applied Physics 108, 033706, 2010, 7 pages. [cited by applicant]
Liutauras Storasta and Hidekazu Tsuchida, “Reduction of traps and improvement of carrier lifetime in 4H—SiC epilayers by ion implantation”, Applied Physics Letters 90, 062116, 2007, 4 pages. [cited by applicant]
P. Fiorenza et al., “SiO2/4H—SiC interface doping during post-deposition-annealing of the oxide in N2O or POCI3”, Applied Physics Letters 103, 153508, 2013, 5 pages. [cited by applicant]
P. Jamet and S. Dimitrijev, “Physical properties of N2O and NO-nitrided gate oxides grown in 4H SiC”, Applied Physics Letters, vol. 79, No. 4, 2001, 4 pages. [cited by applicant]
T. Sledziewski et al., “Reduction of density of 4H—SiC/SiO2 interface traps by pre-oxidation phosphorus implantation”, Materials Science Forum vols. 778-780, 2014, 4 pages. [cited by applicant]
U. Gerstmann et al., “Formation and annealing of nitrogen-related complexes in SiC”, Physical Review B 67, 205202, 2003, 8 pages. [cited by applicant]
Yasuto Hijikata et al., “A Kinetic Model of Silicon Carbide Oxidation Based on the Interfacial Silicon and Carbon Emission Phenomenon”, Applied Physics Express 2, (2009) 021203, 2009, 3 pages. [cited by applicant]
International Preliminary Report on Patentability issued in related PCT/EP2023/052132, dates Jun. 26, 2024, 32 pages. [cited by applicant]