IP Library Granted Patent US 9,136,365
Granted Patent B2
US 9,136,365 · App. 13/716,640 · Granted Sep 15, 2015

Power devices and method for manufacturing the same

Inventors: Jae Hoon Lee (Suwon-si, KR); Ki Se Kim (Suwon-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H01L29/78H01L29/0619H01L29/267H01L29/6606H01L29/66068H01L29/66477H01L29/872H01L29/1608H01L29/2003H01L29/45H01L29/47
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Quick Facts
Patent No.
US 9,136,365
App. No.
13/716,640
Granted
Sep 15, 2015
Kind
B2
Abstract

A power device includes a substrate, a silicon carbide (Si x C 1-x ) layer on one surface of the substrate, wherein 0<x<1, and a re-grown gallium nitride (GaN) layer formed by etching a part of the Si x C 1-x layer and growing GaN from an etched area of the Si x C 1-x layer.

Claims (40)

1. A power device, comprising:

a substrate;

a silicon carbide (Si x C 1-x ) layer on one surface of the substrate, wherein 0<x<1, the Si x C 1-x layer including an etched area, the etched area of the Si x C 1-x layer being in a form of a depression in the Si x C 1-x layer; and

a re-grown gallium nitride (GaN) layer grown from the etched area of the Si x C 1-x layer such that the re-grown GaN layer fills the etched area of the Si x C 1-x layer and directly contacts a bottom and sides of the Si x C 1-x layer in the etched area.

2. The power device as claimed in claim 1 , wherein:

the substrate is an n-type SiC substrate, and

the re-grown GaN layer is a p-GaN layer doped with p-type impurities.

3. The power device as claimed in claim 2 , wherein the power device is a Schottky barrier diode (SBD) and further comprises:

a first electrode on the Si x C 1-x layer; and

a second electrode on another surface of the substrate, the other surface being opposite to the one surface on which the Si x C 1-x layer is located.

4. The power device as claimed in claim 3 , wherein the Si x C 1-x layer is an n-type Si x C 1-x layer doped with n-type impurities.

5. The power device as claimed in claim 2 , wherein a doping concentration of the p-type impurities of the p-GaN layer is about 1.0×10 16 /cm 3 to about 1.0×10 20 /cm 3 .

6. The power device as claimed in claim 1 , wherein:

the substrate is a p-type SiC layer, and

the re-grown GaN layer is an n-GaN layer doped with n-type impurities.

7. The power device as claimed in claim 6 , wherein the power device is a field effect transistor (FET) and further comprises:

a gate electrode disposed on the Si x C 1-x layer; and

a source electrode and a drain electrode on the n-GaN layer.

8. The power device as claimed in claim 7 , wherein the Si x C 1-x layer is a p-type Si x C 1-x layer doped with p-type impurities.

9. The power device as claimed in claim 6 , wherein a doping concentration of the n-type impurities of the n-GaN layer is about 1.0×10 16 /cm 3 to about 1.0×10 20 /cm 3 .

10. The power device as claimed in claim 1 , wherein a top surface of the re-grown gallium nitride (GaN) layer is coplanar with a top surface of the Si x C 1-x layer.

11. A manufacturing method for a power device, the manufacturing method comprising:

forming a silicon carbide (Si x C 1-x ) layer on one surface of a substrate, wherein 0<x<1;

etching a part of the Si x C 1-x layer to provide an etched area, the etched area being in a form of a depression in the Si x C 1-x layer; and

growing gallium nitride (GaN) from the etched area of the Si x C 1-x layer to form a re-grown (GaN) layer, the re-grown GaN layer filling the etched area of the Si x C 1-x layer and directly contacting a bottom and sides of the etched area of the Si x C 1-x layer.

12. The manufacturing method as claimed in claim 11 , wherein the growing of GaN from the etched area of the Si x C 1-x layer to form the re-grown GaN layer is performed within a temperature range of about 1,000° C. to about 1,200° C.

13. The manufacturing method as claimed in claim 11 , wherein:

the substrate is an n-type SiC substrate, and

the re-grown GaN layer is a p-GaN layer doped with p-type impurities.

14. The manufacturing method as claimed in claim 13 , further comprising:

forming a first electrode on the re-grown GaN layer and the Si x C 1-x layer such that the first electrode is in contact with the re-grown GaN layer; and

forming a second electrode on another surface of the substrate, the other surface being opposite to the one surface on which the Si x C 1-x layer is disposed.

15. The manufacturing method as claimed in claim 14 , wherein the Si x C 1-x layer is an n-type Si x C 1-x layer doped with n-type impurities.

16. The manufacturing method as claimed in claim 11 , wherein

the substrate is a p-type SiC substrate, and

the re-grown GaN layer is an n-GaN layer doped with n-type impurities.

17. The manufacturing method as claimed in claim 16 , further comprising:

forming a gate electrode on the Si x C 1-x layer; and

forming a source electrode and a drain electrode on the n-GaN layer.

18. The manufacturing method as claimed in claim 17 , wherein the Si x C 1-x layer is a p-type Si x C 1-x layer doped with p-type impurities.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2012
From: LEE, JAE-HOON; KIM, KI SE
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 029481/0568 →
Priority Claims (1)
KR 10-2011-0144859 · Dec 28, 2011 · national
Continuity (1)
Related Publication 20130168698A1 · Jul 4, 2013