Device, method and system for providing branch information to an instruction fetch unit based on a detection of a fall-through event wherein multiple fetched instructions comprise a branch instruction
Techniques and architectures for determining a target of a branch instruction. In an embodiment, a processor core detects a fall through event wherein multiple fetched instructions comprise one or more branch instructions. Based on the fall through event, a repository is provided with respective branch information for each of the one or more branch instructions. The repository functions as a cache that is available to an evaluation circuit at an instruction fetch stage of the processor core. Branch information at the repository is accessible to facilitate a relatively early identification of an instruction as being of a branch instruction type. In another embodiment, the early identification enables re-steering of a speculative execution sequence.
1 . An integrated circuit (IC) comprising:
a detector circuit to be coupled to a decoder circuit, the detector circuit to monitor operations of the decoder circuit to detect an event wherein multiple instructions are fetched, wherein the multiple instructions comprise a branch instruction; and
an instruction fetch circuit to be coupled to a branch prediction circuit, and to the decoder circuit, the instruction fetch circuit comprising:
a repository coupled to the detector circuit, wherein, based on the event, the repository is to receive from the detector circuit branch information which corresponds to the branch instruction; and
an evaluation circuit coupled to the repository, the evaluation circuit to:
receive an indication that the branch instruction is to be fetched, wherein the indication is based on an output of the branch prediction circuit;
based on the indication, perform a search of the repository to access the branch information; and
based on the search, send to the branch prediction circuit a signal to clear a prediction of an instruction to be executed after the branch instruction.
2 . The IC of claim 1 , wherein:
the branch information comprises an identifier of another instruction as a target of the branch instruction; and
based on the search, the evaluation circuit is further to output a signal to fetch the other instruction.
3 . The IC of claim 1 , wherein the signal is to clear one or more entries from a branch target buffer which is coupled to the branch prediction circuit.
4 . The IC of claim 1 , wherein, based on the search, the evaluation circuit is further to send another signal to clear one or more entries of a prediction queue which is coupled between the branch prediction circuit and the evaluation circuit.
5 . The IC of claim 1 , wherein, based on the event, the detector circuit is to provide to the repository respective branch information for each direct call instruction of the multiple instructions.
6 . The IC of claim 5 , wherein:
each direct call instruction of the multiple instructions is to correspond to a different respective return instruction of one or more return instructions; and
wherein, based on the event, the detector circuit is to provide to the repository respective branch information for each of the one or more return instructions.
7 . The IC of claim 1 , wherein:
the instruction fetch circuit is to fetch instructions from a first cache;
the repository comprises a second cache; and
the detector circuit is to cache the branch information to a line of the second cache based on the event.
8 . The IC of claim 7 , wherein the line of the second cache is to be indexed based on a corresponding line of the first cache.
9 . The IC of claim 7 , wherein:
for each branch instruction of the multiple instructions which is of a direct call instruction type or of a return instruction type, the detector circuit is to cache branch information, which corresponds to the branch instruction, to a different respective line of the second cache based on the event.
10 . A system comprising:
a processor core comprising:
a detector circuit to be coupled to a decoder circuit, the detector circuit to monitor operations of the decoder circuit to detect an event wherein multiple instructions are fetched, wherein the multiple instructions comprise a branch instruction; and
an instruction fetch circuit to be coupled to a branch prediction circuit, and to the decoder circuit, the instruction fetch circuit comprising:
a repository coupled to the detector circuit, wherein, based on the event, the repository is to receive from the detector circuit branch information which corresponds to the branch instruction; and
an evaluation circuit coupled to the repository, the evaluation circuit to:
receive an indication that the branch instruction is to be fetched, wherein the indication is based on an output of the branch prediction circuit;
based on the indication, perform a search of the repository to access the branch information; and
based on the search, send to the branch prediction circuit a signal to clear a prediction of an instruction to be executed after the branch instruction;
a memory controller coupled to the processor core; and
a memory coupled to the memory controller, the memory to store information which is accessible to the processor core via the memory controller.
11 . The system of claim 10 , wherein:
the branch information comprises an identifier of another instruction as a target of the branch instruction; and
based on the search, the evaluation circuit is further to output a signal to fetch the other instruction.
12 . The system of claim 10 , wherein the signal is to clear one or more entries from a branch target buffer which is coupled to the branch prediction circuit.
13 . The system of claim 10 , wherein, based on the event, the detector circuit is to provide to the repository respective branch information for each direct call instruction of the multiple instructions.
14 . The system of claim 10 , wherein:
the instruction fetch circuit is to fetch instructions from a first cache;
the repository comprises a second cache; and
the detector circuit is to cache the branch information to a line of the second cache based on the event.
15 . The system of claim 14 , wherein the line of the second cache is to be indexed based on a corresponding line of the first cache.
16 . A method at a processor, the method comprising:
monitoring operations of a decoder circuit, wherein the monitoring detects an event wherein multiple instructions are fetched, wherein the multiple instructions comprise a branch instruction;
based on the event, providing branch information to a repository of an instruction fetch circuit, wherein the branch information corresponds to the branch instruction; and
with an evaluation circuit of the instruction fetch circuit:
receiving an indication that the branch instruction is to be fetched, wherein the indication is based on an output of a branch prediction circuit;
based on the indication, performing a search of the repository to access the branch information; and
based on the search, sending to the branch prediction circuit a signal to clear a prediction of an instruction to be executed after the branch instruction.
17 . The method of claim 16 , wherein:
the branch information comprises an identifier of another instruction as a target of the branch instruction; and
the method further comprises:
with the evaluation circuit, outputting a signal to fetch the other instruction based on the search.
18 . The method of claim 16 , wherein the signal is to clear one or more entries from a branch target buffer which is coupled to the branch prediction circuit.
19 . The method of claim 16 , wherein, based on the event, the repository receives respective branch information for each direct call instruction of the multiple instructions.
20 . The method of claim 19 , wherein:
each direct call instruction of the multiple instructions corresponds to a different respective return instruction of one or more return instructions; and
wherein, based on the event, the repository receives respective branch information for each of the one or more return instructions.