Granted Patent B2

US 12,360,768 · App. 17/553,780 · Granted Jul 15, 2025

Inventors: Anant Vithal Nori (Bangalore, IN); Prathmesh Kallurkar (Bangalore, IN); Sreenivas Subramoney (Bangalore, IN); Niranjan Kumar Soundararajan (Bengaluru, IN)

Assignee: Intel Corporation

G06F9/3802

Abstract

Claims (24)

1. An apparatus comprising:

a first storage structure to store a reference to a code line in response to a request to be received from a cache;

a second storage structure to store a reference to the code line in response to an update to an Instruction Dispatch Queue (IDQ); and

logic circuitry to control additional code line fetch operations based at least in part on a comparison of a number of ongoing speculative code fetches and a determination that the code line is speculative, wherein the code line is to be considered as speculative in response to one of: (a) a hit in the first storage structure for the code line and a miss in the second storage structure for the code line; and (b) a hit in the second storage structure for the code line and a miss in the first storage structure for the code line.

2. The apparatus of claim 1 , wherein the logic circuitry is to disallow the additional code line fetch operations based at least in part on a determination that the number of ongoing speculative code fetches has reached a threshold value and the determination that the code line is speculative.

3. The apparatus of claim 1 , wherein the logic circuitry is to allow the additional code line fetch operations based at least in part on a determination that the number of ongoing speculative code fetches has not reached a threshold value and the determination that the code line is speculative.

4. The apparatus of claim 1 , wherein the logic circuitry is to control the additional code line fetch operations for code lines that cause a miss in an instruction cache.

5. The apparatus of claim 1 , wherein the logic circuitry is to control the additional code line fetch operations based at least in part on the comparison of the number of ongoing speculative code fetches in a front end of a processor.

6. The apparatus of claim 1 , wherein the first storage structure comprises a front end Bloom filter.

7. The apparatus of claim 1 , wherein the second storage structure comprises an IDQ Bloom filter.

8. The apparatus of claim 1 , wherein the reference to the code line comprises a virtual address of the code line.

9. The apparatus of claim 1 , wherein the cache is a Level 2 (L2) cache.

10. The apparatus of claim 1 , wherein the second storage structure is to store an indication of at least one of one or more instructions and one or more micro-operations that have been allocated in the IDQ.

11. The apparatus of claim 10 , wherein the IDQ is to store at least one of an instruction and a micro-operation to be allocated in a pre-execution stage of a processor pipeline.

12. The apparatus of claim 1 , wherein the code line is to store at least one of an instruction or a micro-operation.

13. The apparatus of claim 1 , wherein a processor, having one or more processor cores, comprises one or more of: the logic circuitry, the first storage structure, and the second storage structure.

14. One or more non-transitory computer-readable media comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to cause:

a first storage structure to store a reference to a code line in response to a request to be received from a cache;

a second storage structure to store a reference to the code line in response to an update to an Instruction Dispatch Queue (IDQ); and

logic circuitry to control additional code line fetch operations based at least in part on a comparison of a number of ongoing speculative code fetches and a determination that the code line is speculative, wherein the code line is to be considered as speculative in response to one of: (a) a hit in the first storage structure for the code line and a miss in the second storage structure for the code line; and (b) a hit in the second storage structure for the code line and a miss in the first storage structure for the code line.

15. The one or more computer-readable media of claim 14 , further comprising one or more instructions that when executed on the processor configure the processor to perform one or more operations to cause the logic circuitry to disallow the additional code line fetch operations based at least in part on a determination that the number of ongoing speculative code fetches has reached a threshold value and the determination that the code line is speculative.

16. The one or more computer-readable media of claim 15 , further comprising one or more instructions that when executed on the processor configure the processor to perform one or more operations to cause the logic circuitry to allow the additional code line fetch operations based at least in part on a determination that the number of ongoing speculative code fetches has not reached a threshold value and the determination that the code line is speculative.

17. The one or more computer-readable media of claim 14 , further comprising one or more instructions that when executed on the processor configure the processor to perform one or more operations to cause the logic circuitry to control the additional code line fetch operations for code lines that cause a miss in an instruction cache.

18. The one or more computer-readable media of claim 14 , further comprising one or more instructions that when executed on the processor configure the processor to perform one or more operations to cause the logic circuitry to control the additional code line fetch operations based at least in part on the comparison of the number of ongoing speculative code fetches in a front end of a processor.

Assignments (1)

Continuity (1)

References Cited (142)