Dynamic management of virtual memory blocks exempted from cache memory access
A computer-implemented method for identification of cache memory transiency may include identifying, with a processor, a virtual memory address section having a virtual memory address, determining, via the processor, a classification of cache memory transiency of the virtual memory address section, and determining, with the processor, based on the classification of cache memory transiency, a cache exemption status.
1. A computer-implemented method for identification of cache memory transiency comprising:
identifying, with a processor, a virtual memory address section having a virtual memory address, wherein the virtual memory address comprises a plurality of region index fields and a byte index;
determining, via the processor, a classification of cache memory transiency of the virtual memory address section;
wherein the classification of cache memory transiency comprises one of a group of values comprising transient, not transient, somewhat transient, mostly transient, and never transient; and
wherein the classification of the cache memory transiency is indicative of a level of eligibility for cache exemption that is greater than or less than another control in a leaf table entry and is indicated as greater than or less than previous controls for the leaf table entry, and wherein a data portion having a greater value relative to another control is subject to caching, and a control having a smaller value relative to another control is not subject to caching; and
determining, with the processor, based on the classification of cache memory transiency, a cache exemption status.
2. The computer-implemented method of claim 1 , wherein the classification of the cache memory transiency is determined based on whether the memory section comprises one or more memory pointers.
3. The computer-implemented method of claim 1 , wherein the cache exemption status is indicative of whether a block of virtual memory should be placed into the cache memory.
4. The computer-implemented method of claim 1 , wherein the virtual memory address section comprises one or more of page information, region information and segment information.
5. The computer-implemented method of claim 1 , wherein the classification of the cache memory transiency is indicative of one or more memory allocation actions based on a relative numeric priority compared to another table entry of a plurality of table entries.
6. A system for identification of cache memory transiency comprising a cache memory and a processor having access to the cache memory and configured to:
identify a virtual memory address section of the cache memory having a virtual memory address, wherein the virtual memory address comprises a plurality of region index fields and a byte index;
determine a classification of cache memory transiency of the virtual memory address section;
wherein the classification of cache memory transiency comprises one of a group of values comprising transient, not transient, somewhat transient, mostly transient, and never transient
wherein the classification of the cache memory transiency is indicative of a level of eligibility for cache exemption that is greater than or less than another control in a leaf table entry and is indicated as greater than or less than previous controls for the leaf table entry, and wherein a data portion having a greater value relative to another control is subject to caching, and a control having a smaller value relative to another control is not subject to caching; and
determine, based on the classification of cache memory transiency, a cache exemption status.
7. The system of claim 6 , wherein the cache exemption status is indicative of whether a block of virtual memory should be saved into the cache memory.
8. The system of claim 6 , wherein the classification of the cache memory transiency is indicative of whether the address is a memory location pointer.
9. The system of claim 6 , wherein the virtual memory address section comprises one or more of page information, region information and segment information.
10. A non-transitory computer-readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method for identification of cache memory transiency, the method comprising:
identifying, with a processor, a virtual memory address section having a virtual memory address, wherein the virtual memory address comprises a plurality of region index fields and a byte index;
determining a classification of cache memory transiency of the virtual memory address section;
wherein the classification of cache memory transiency comprises one of a group of values comprising transient, not transient, somewhat transient, mostly transient, and never transient; and
wherein the classification of the cache memory transiency is indicative of a level of eligibility for cache exemption that is greater than or less than another control in a leaf table entry and is indicated as greater than or less than previous controls for the leaf table entry, and wherein a data portion having a greater value relative to another control is subject to caching, and a control having a smaller value relative to another control is not subject to caching; and
determining, with the processor, based on the classification of cache memory transiency, a cache exemption status.
11. The non-transitory computer-readable storage medium of claim 10 , wherein the classification of the cache memory transiency is determined based on whether the memory section comprises one or more memory pointers.
12. The non-transitory computer-readable storage medium of claim 10 , wherein the cache exemption status is indicative of whether a block of virtual memory should be placed into the cache memory.
13. The non-transitory computer-readable storage medium of claim 10 , wherein the virtual memory address section comprises one or more of page information, region information and segment information.